Xilinx Alveo U50 User Manual

The detailed FPGA connecons for this feature are documented in the Alveo U50 accelerator
card Xilinx Design Constraints (XDC) le, referenced in Appendix A: Xilinx Design Constraints
(XDC) File.
SFP-DD Module Connectors
The Alveo U50 accelerator cards host two small form-factor pluggable (SFP-DD) connectors that
accept an array of opcal modules. Each connector is housed within a single cage assembly and
are accessible through the I2C interface.
Access from the FPGA to SFP-DD modules and support for miscellaneous SFP-DD signals is
provided through the satellite controller. For more informaon about the SFP-DD module, see
SFP-DD Specicaon.
• MGTREFCLK0 is from SI5394 with programmable output frequencies
• Maximum SFP-DD power is 3.5W per port
• The target for SFP-DD channel length is 4 inches maximum
Note: The Alveo U50 card that includes one QSFP interface is producon qualied for deployment. The
Alveo U50DD ES3 card that supports two SFP-DD interfaces is not recommended for deployment.
Detailed FPGA connecons for this feature are documented in the Alveo U50 accelerator card
XDC le, referenced in Appendix A: Xilinx Design Constraints (XDC) File.
I2C Bus
The Alveo U50 accelerator cards implement an I2C bus network.
Status LEDs
The U50 has two set of LEDs:
1. Card status LEDs
2. Ethernet status LEDs
Card status LEDs are visible through a cutout in the PCIe end bracket and are dened in the
following table. Producon cards will not have board status LEDs.
Chapter 4: Card Component Description
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 18
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Xilinx Alveo U50 Specifications

General

Brand	Xilinx
Model	Alveo U50
Category	Computer Hardware
Language	English