Xilinx SmartLynq Plus User Manual

Chapter 4
USB 3.0 Host Connection
The SmartLynq+ Module can be accessed by a host system using the USB 3.0 connecon. When
accessing the module through the USB 3.0 interface, the host establishes a network interface
used by applicaons such as Vivado
®
Design Suite to communicate with the module. Vivado
Design Suite version 2020.2 or later is required to support the SmartLynq+ Module for USB3.0
and HSDP.
Note: The SmartLynq+ Module is not powered by the USB 3.0 interface and must have the power cable
plugged in and supplying power prior to use.
Minimum Host System Requirements
These are the supported operang systems on x86 and x86-64 processor architectures:
• Microso Windows Professional/Enterprise 10.0 1809 Update; 10.0 1903 Update; 10.0 1909
Update; 10.0 2004 Update
• Red Hat Enterprise Workstaon/Server 7.4 - 7.8, and 8.2 (64-bit), English/Japanese
• CentOS 7.4 - 7.8, and 8.2 (64-bit), English/Japanese
• Ubuntu Linux 16.04.5 LTS;16.04.6 LTS; 18.04.1 LTS; 18.04.2 LTS, 18.04.3 LTS; 18.04.4 LTS;
and 20.04 LTS (64-bit), English/Japanese
Default USB 3.0 IP Setting
The default factory image seng for the SmartLynq+ Module USB 3.0 interface is 10.0.0.2.
Ensure that 10.0.0.2 IP on the host machine can be used to form a local network for the
SmartLynq+ Module. If necessary, you can change this seng but you sll need to have the host
inially access 10.0.0.2 to be able to change the USB 3.0 IP factory seng.
Chapter 4: USB 3.0 Host Connection
UG1514 (v1.0) March 8, 2021 www.xilinx.com
SmartLynq Module+ 12
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Xilinx SmartLynq Plus Specifications

General

Brand	Xilinx
Model	SmartLynq Plus
Category	Network Hardware
Language	English