Xilinx SmartLynq Plus User Manual

Chapter 1
Overview
The Xilinx
®
SmartLynq+ Module is a high-speed debug and trace module, primarily targeng the
Versal™ adapve compute acceleraon plaorm (ACAP). It drascally improves conguraon and
trace speed. For trace capture, the SmartLynq+ module is capable of speeds up to 10 Gb/s by
means of its high-speed debug port (HSDP), which is 100 mes faster than standard JTAG. Faster
iteraons and repeve downloads increase development producvity and reduce the design
cycle.
Features
The SmartLynq+ Module provides the following features:
• Super-fast download speed, maximize development producvity for faster iteraons
• High-speed trace with enhanced visibility, up to 14 GB of trace memory for execuon history
• Full visibility for heterogeneous architectures, in-depth debug for Hard IP and Engines in
Versal ACAP
• Cohesive and me-related debug of all subsystems
• Flexible and smart debug plaorm with features such as smart ltering and a soware-
programmable built-in debugger
• Sharable debug plaorm with unied view for remote, mul-user environment
Note: The SmartLynq+ Module is not supported by Xilinx ISE
®
tools.
Description
The SmartLynq+ Module oers high-bandwidth connecvity to allow heterogenous system
debug and trace of Versal ACAP-based applicaons. It provides all of the desired connecons for
programming, debug and trace. JTAG can be a direct connecon with PC4 connector,
MICTOR-38 connector, or via USB-C when used along with HSDP.
Chapter 1: Overview
UG1514 (v1.0) March 8, 2021 www.xilinx.com
SmartLynq Module+ 5
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Xilinx SmartLynq Plus Specifications

General

Brand	Xilinx
Model	SmartLynq Plus
Category	Network Hardware
Language	English