Xilinx Virtex-7 FPGA VC7222 IBERT User Manual

18 www.xilinx.com VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Chapter 1: VC7222 IBERT Getting Started Guide
Starting the SuperClock-2 Module
The IBERT demonstration designs use an integrated VIO core to control the clocks on the
SuperClock-2 module. The SuperClock-2 module features two clock-source components:
• Always-on Si570 crystal oscillator
• Si5368 jitter-attenuating clock multiplier
Outputs from either source can be used to drive the transceiver reference clocks. To start
the SuperClock-2 module:
1. The Vivado Design Suite Hardware window shows the System ACE and the
XC7VH580T device. The XC7VH580T device is reported as programmed when an SD
card is used to program the FPGA during power reset (Figure 1-13). If the SD card is
not available to program the XC7VH580T device, select the device, and in the
Hardware Device Properties window, enter the file path to the programming and the
probes files associated with the Q115 IBERT design. The files are in the extracted IBERT
files:
../vc7222_ibert_q115_325.bit
../vc7222_ibert_q115_debug_nets.ltx
X-Ref Target - Figure 1-13
Figure 1-13: Adding the Probes File
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Xilinx Virtex-7 FPGA VC7222 IBERT Specifications

General

Brand	Xilinx
Model	Virtex-7 FPGA VC7222 IBERT
Category	Motherboard
Language	English