Xilinx Virtex-7 FPGA VC7222 IBERT User Manual

VC7222 IBERT Getting Started Guide www.xilinx.com 55
UG971 (v5.0) June 12, 2014
Chapter 3
Creating the GTZ IBERT Core
This section provides a procedure to create the GTZ IBERT core with integrated
SuperClock-2 controller. Vivado® Design Suite 2014.2 is required to rebuild the design
shown here.
For more details on generating IBERT cores, see the Vivado Design Suite User Guide:
Programming and Debugging (UG908) [Ref 3].
Note:
See steps 1–5 in Chapter 2, Creating the GTH IBERT Core to learn how to create a new IP
core.
1. In the IP Catalog window expand the Debug & Verification folder, then expand
the Debug folder. Double-click or right-click the IBERT 7 Series GTZ to run the
GTZ configuration wizard (Figure 3-1).
X-Ref Target - Figure 3-1
Figure 3-1: IP Catalog
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Xilinx Virtex-7 FPGA VC7222 IBERT Specifications

General

Brand	Xilinx
Model	Virtex-7 FPGA VC7222 IBERT
Category	Motherboard
Language	English