Xilinx Virtex-7 FPGA VC7222 IBERT User Manual

54 www.xilinx.com VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Chapter 2: Creating the GTH IBERT Core
17. In the Program Manager, under Program and Debug, click Generate Bitstream
(Figure 2-15). A window pops up asking if it is ok to launch implementation. Click
Yes.
18. When the Bitstream Generation Completed dialog window appears, click Cancel
(Figure 2-16).
19. Navigate to the
..\ibert_7series_gtz_0\ibert_7series_gtz_0_example\ibert_7serie
s_gtz_0_example.runs\impl_1 directory to locate the generated bitstream.
X-Ref Target - Figure 2-15
Figure 2-15: Generate Bitstream
X-Ref Target - Figure 2-16
Figure 2-16: Bitstream Generation Completed
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8*BFBB
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Xilinx Virtex-7 FPGA VC7222 IBERT Specifications

General

Brand	Xilinx
Model	Virtex-7 FPGA VC7222 IBERT
Category	Motherboard
Language	English