Xilinx Virtex-7 FPGA VC7222 IBERT User Manual

VC7222 IBERT Getting Started Guide www.xilinx.com 53
UG971 (v5.0) June 12, 2014
16. When the Synthesized Design opens, select dbg_hub in the Netlist window, then
select the Debug Core Options tab in the Cell Properties window. Change
C_USER_SCAN_CHAIN* to 2 (Figure 2-14). Click File > Save Constraints.
X-Ref Target - Figure 2-14
Figure 2-14: Debug Core Options for dbg_hub
8*BFBB
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Xilinx Virtex-7 FPGA VC7222 IBERT Specifications

General

Brand	Xilinx
Model	Virtex-7 FPGA VC7222 IBERT
Category	Motherboard
Language	English