Xilinx XC4000 Series User Manual

September 18, 1996 (Version 1.04) 4-5
XC4000-Series Features
Note: XC4000-Series devices described in this data sheet
include the XC4000E, XC4000EX, XC4000L, and
XC4000XL. This information does not apply to the older
Xilinx families: XC4000, XC4000A, XC4000D or XC4000H.
For information on these devices, see the Xilinx W
EB
LINX
at http://www.xilinx.com.
• Third Generation Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Fully PCI compliant (speed grades -3 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- 8 global low-skew clock or signal distribution
networks
• System Performance to 66 MHz
• Flexible Array Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output (4 mA per
XC4000L output)
• Configured by Loading Binary File
- Unlimited reprogrammability
• Readback Capability
• Backward Compatible with XC4000 Devices
•XACT
step Development System runs on '386/'486/
Pentium-type PC, Sun-4, and Hewlett-Packard 700
series
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
- RAM/ROM compiler
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000L: Low-Voltage Versions of XC4000E devices
• XC4000XL: Low-Voltage Versions of XC4000EX
devices
Additional XC4000EX/XL Features
• Highest Capacity — Over 130,000 Usable Gates
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
• Buffered Interconnect for Maximum Speed
• New Latch Capability in Configurable Logic Blocks
• Improved VersaRing
TM
I/O Interconnect for Better Fixed
Pinout Flexibility
• Flexible New High-Speed Clock Network
- 8 additional Early Buffers for shorter clock delays
- 4 additional FastCLK
TM
buffers for fastest clock input
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on
Device Outputs
• High-Speed Parallel Express
TM
Configuration Mode
• Improved I/O Setup and Clock-to-Output with FastCLK
and Global Early Buffers
• 4 Additional Address Bits in Master Parallel
Configuration Mode
Introduction
XC4000-Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of eleven years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated soft-
ware to achieve fully automated implementation of com-
plex, high-density, high-performance designs.
The XC4000 Series currently has 19 members, as shown
in Table 1.
XC4000 Series
Field Programmable Gate Arrays
September 18, 1996 (Version 1.04) Product Specification


Xilinx XC4000 Series Specifications

General

Brand	Xilinx
Model	XC4000 Series
Category	Controller
Language	English