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Xilinx XC4000 Series User Manual

Xilinx XC4000 Series
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XC4000 Series Field Programmable Gate Arrays
4-40 September 18, 1996 (Version 1.04)
Octal I/O Routing (XC4000EX only)
Between the XC4000EX CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See Figure 34.)
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buff-
ers are staggered, so each line goes through a buffer at
every eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Figure 34.
IOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and dou-
ble-length lines, quads, and longlines within the CLB array.
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Segment with nearest buffer
connects to segment with furthest buffer
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
X6607
Figure 34: XC4000EX Octal I/O Routing

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Xilinx XC4000 Series Specifications

General IconGeneral
BrandXilinx
ModelXC4000 Series
CategoryController
LanguageEnglish

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