Xilinx XC4000 Series User Manual

XC4000 Series Field Programmable Gate Arrays
4-6 September 18, 1996 (Version 1.04)
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note: Throughout the functional descriptions in this docu-
ment, references to the XC4000E device family include the
XC4000L, and references to the XC4000EX device family
include the XC4000XL, unless explicitly stated otherwise.
References to the XC4000 Series include the XC4000E,
XC4000EX, XC4000L, and XC4000XL families. All func-
tionality in low-voltage families is the same as in the corre-
sponding 5-Volt family, except where numerical references
are made to timing, power, or current-sinking capability.
Description
XC4000-Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA from an external device
(slave, peripheral and Express modes).
XC4000-Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floorplanning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000EX, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Table 2 shows density and performance for a few common
circuit functions that can be implemented in XC4000-Series
devices.
Table 1: XC4000-Series Field Programmable Gate Arrays
Device
Max Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and RAM)*
CLB
Matrix
Total
Logic
Blocks
Number
of
Flip-Flops
Max.
Decode
Inputs
per side
Max.
User I/O
XC4003E 3,000 3,200 2,000 - 5,000 10 x 10 100 360 30 80
XC4005E/L 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112
XC4006E 6,000 8,192 4,000 - 12,000 16 x 16 256 768 48 128
XC4008E 8,000 10,368 6,000 - 15,000 18 x 18 324 936 54 144
XC4010E/L 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160
XC4013E/L 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192
XC4020E 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 84 224
XC4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256
XC4028EX/XL 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256
XC4036EX/XL 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 108 288
XC4044EX/XL 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 120 320
XC4052XL 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 132 352
XC4062XL 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 144 384
Larger Devices Available in the First Half of 1997

Xilinx XC4000 Series Specifications

General

Brand	Xilinx
Model	XC4000 Series
Category	Controller
Language	English