Xilinx ZC706 User Manual

ZC706 Evaluation Board User Guide www.xilinx.com 45
UG954 (v1.5) September 10, 2015
Feature Descriptions
Table 1-17 lists the GTX Bank 112 interface connections between the AP SoC U1 and PCIe
4-lane connector P4.
For additional information about Zynq-7000 PCIe functionality, see 7SeriesFPGAs
Integrated Block for PCI Express Product Guide for Vivado Design Suite (
PG054). Additional
information about the PCI Express standard is available [Ref 22].
Table 1-16: AP SoC GTX Bank 112 Interface Connections to PCIe 4-Lane Connector P4
Transceiver
Bank
AP SoC U1 Pin
Number
AP SoC U1 Pin Name Schematic Net Name
PCIe 4-Lane Conn. P4
Pin Number
GTX_BANK_112 T2 MGTPTXP0_112 PCIE_TX3_P A29 (1)
T1 MGTPTXN0_112 PCIE_TX3_N A30 (1)
V6 MGTPRXP0_112 PCIE_RX3_P B27
V5 MGTPRXN0_112 PCIE_RX3_N B28
R4 MGTPTXP1_112 PCIE_TX2_P A25 (1)
R3 MGTPTXN1_112 PCIE_TX2_N A26 (1)
U4 MGTPRXP1_112 PCIE_RX2_P B23
U3 MGTPRXN1_112 PCIE_RX2_N B24
P2 MGTPTXP2_112 PCIE_TX1_P A21 (1)
P1 MGTPTXN2_112 PCIE_TX1_N A22 (1)
T6 MGTPRXP2_112 PCIE_RX1_P B19
T5 MGTPRXN2_112 PCIE_RX1_N B20
N4 MGTPTXP3_112 PCIE_TX0_P A16 (1)
N3 MGTPTXN3_112 PCIE_TX0_N A17 (1)
P6 MGTPRXP3_112 PCIE_RX0_P B14
P5 MGTPRXN3_112 PCIE_RX0_N B15
N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1)
N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1)
R8 MGTREFCLK1P_112 NC NA
R7 MGTREFCLK1N_112 NC NA
Notes:
1. PCIE_TXn_P/N and PCIE_CLK_Q0_P/N are capacitively coupled to the PCIe edge connector P4.
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Xilinx ZC706 Specifications

General

Brand	Xilinx
Model	ZC706
Category	Motherboard
Language	English