Xilinx ZC706 User Manual

ZC706 Evaluation Board User Guide www.xilinx.com 88
UG954 (v1.5) September 10, 2015
Jumpers
18 J72 MIO Select Header MIO4 (Note: DIP SW11 pole 3
affects this signal)
1-2 QSPI0_IO4 = MIO2_SELECT 15
19 J73 MIO Select Header MIO5 (Note: DIP SW11 pole 4
affects this signal)
1-2 QSPI0_IO5 = MIO2_SELECT 15
20 J74 MIO Select Header MIO6 (Note: DIP SW11 pole 5
affects this signal)
1-2 QSPI0_CLK = MIO6_SELECT 15
HDR_1 X 3
21 J43 PS_SRST_B Select Header 1-2 PS_SRST_B = PS_SRST_B_SW
(MAX16025 U8 pin 10)
15
22 J44 PS_POR_B Select Header 1-2 PS_POR_B = PS_POR_B_SW
(MAX16025 U8 pin 11)
15
23 J45 U51 Ethernet PHY CONFIG3 pin 3 1K pull-up to 1.8V
or 1 KΩ pull-down to GND Select Header
1-2 U51 pin 3 CONFIG3 = 1 (p/u
to 1.8V)
29
24 J46 U51 Ethernet PHY CONFIG2 pin 2 tie to 1.8V or
LED0 Select Header
OPEN J9 sets U51 pin 2 CONFIG2
condition
29
25 J47 U51 Ethernet PHY CONFIG3 pin 3 LED1 or LED0
Select Header
OPEN No connection to LED0 or
LED1, J45 sets U51 pin 3
CONFIG3 condition
29
26 J48 U12 USB3320 2.0 MODE Select Header 2-3 HOST/OTG Mode selected 31
27 J49 USB 2.0 Micro-B connector J2 ID pin 4 function
Select Header
1-2 J2 ID pin 4 connected to
USB3320 U12 pin 23 ID
31
28 J50 USB_VBUS_SEL 1uF/120 uF capacitor to GND Select
Header
2-3 USB_VBUS_SEL net has 120
uF to GND
31
29 J51 USB 2.0 Micro-B connector J2 ID shield pins
connection Select Header
1-2 J2 shield pins to GND 31
30 J52 XADC_VREFP source Select Header 1-2 XADC_VREFP = XADC_VREF 35
31 J53 XADC_VCC source Select Header 1-2 XADC_VCC = VCCAUX 1.8V 35
32 J54 U38 REF3012 VREF Vin Select Header 2-3 U38 powered by XADC_VCC
(U14 1.85V)
35
33 J55 SPF+ P2 SFP_RS1 BW Select Header 2-3 LOW BW TX selected 41
34 J56 SPF+ P2 SFP_RS0 BW Select Header 2-3 LOW BW RX selected 41
Table A-2: Default Jumper Settings (Cont ’d)
Jumper
Callout
Jumper Function
Default Jumper
Position
Option Selected
Schematic
0381513
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Xilinx ZC706 Specifications

General

Brand	Xilinx
Model	ZC706
Category	Motherboard
Language	English