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MATRIX SERVSWITCH™
2.5 Cable Requirements
Many switches of this type have what seems like ten million connectors on their
rear panels: one for each CPU’s video cable, one for each keyboard cable, and a
third for each mouse cable. The potential for tangling or mismatching cables is
high.
By contrast, you can connect the Matrix ServSwitch to your CPUs with one CPU
Cable (also called a “CPU Adapter Cable”) for each CPU. This single cable reaches
the CPU’s video-output, keyboard, and mouse ports.
To connect other Matrix ServSwitches, you need two Matrix ServSwitch
Expansion Cables for each chassis-to-chassis connection. (Each chassis also needs
to have an Expansion Module installed in it.)
Finally, you can connect the Matrix ServSwitch to the shared monitors,
keyboards, and mice with one User Cable (also called an “MKM Adapter Cable”)
for each keyboard/monitor/mouse user station.
The exact variety or varieties of these cables that you’ll need will depend on the
equipment you are connecting for your application. Refer to Appendix B for the
available types of these cables and the corresponding product codes. Also refer to
Chapter 1 and the Caution notice in Section 3.3.1 for information about maximum
cabling distances.
NOTES
SVGA (over longer distances) and XGA video place special demands on
cabling that the regular CPU Cables and User Cables typically cannot
meet. For these applications, you should use coaxial cables that can
carry video signals not only farther but also at
higher resolutions. See
Appendix B and the Caution notice in Section 3.3.1. You’ll also need a “Mac
Adapter for ServSwitch” (KV99MA) for each Mac CPU outputting high-res
(greater than 640 x 480) video.
2.6 Equipment Requirements
If the CPUs you will be controlling through your Matrix ServSwitch are not all of
the same type—especially if you’re using multiplatform Switches and the CPUs
represent completely different hardware platforms (IBM, Sun, etc.)—you will have
to be careful to choose a common monitor, keyboard, and mouse that adequately
support all of the CPUs. For full details, see Section 3.2.
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