About the module Multiplexed GPIO
ConnectCore for i.MX51 Hardware Reference Manual
55
The I2C interface provides the following capabilities:
n Compatibility with I2C bus standard
n Multiple-master operation
n Software programmable for one of 64 different serial clock frequencies
n Software selectable acknowledge bit
n Start and stop signal generation detection
n Repeated START signal generation
n Acknowledge bit generation/detection
n Bus-busy detection
Video subsystem
The i.MX51 processor has a video subsystem that includes the following modules:
n Video Processing Unit (VPU): a multi-standard video encoder/decoder
n Image Processing Unit (IPU): providing connectivity to displays, related processing,
synchronization and control
n TV encoder (TVE) bride: providing optional translation from the digital display interface
supported by the IPU to SDTV analog and some HDTV interfaces
Video Processing Unit (VPU)
The video processing unit of the i.MX51 is a high performance, multistandard video processing unit
that can perform H.264 BP/MP/HP, VC-1 SP/MP/AP, MPEG4 SP/ASP, Divx, RV8/9, and MPEG2 MP
decoding up to 1920 × 1088 resolution. It supports multiple video codecs simultaneously.
The detailed features of the VPU are as follows:
n Multi-standard video codec
l H.264/AVC decoder for baseline profile, main profile and high profile
l VC-1 decoder for simple profile, main profile and advanced profile
l MPEG-4 decoder for simple profile, advanced simple profile except GMC
l H.263 decoder for baseline profile
l Divx Home Theater decoder for profile (version 3.x, 4.x, 5.x, 6.x) and Xvid
l MPEG-2 decoder for main profile @ high level
l RV decoder for profile 8/9/10
l H.264/AVC encoder for baseline profile
l MPEG-4 encoder for simple profile
l H.263 encoder for baseline profile
l MJPEG encoder for baseline profile
l Multiple codec: supports up to 4 decoding/encoding processes simultaneously, each
process can have a different format
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