Intel S5500WB User Manual

Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder
Revision 1.3
Intel order number E53971-004
91
QuickPath Interconnect (QPI)
0xA0h
1
0
1
0 0 0 0 0
QPI Initialization
0xA1h
1
0
1
0 0 0 0
1
QPI Initialization
0xA2h
1
0
1
0 0 0
1
0
QPI Initialization
0xA3h
1
0
1
0 0 0
1 1
QPI Initialization
0xA4h
1
0
1
0 0
1
0 0
QPI Initialization
0xA5h
1
0
1
0 0
1
0
1
QPI Initialization
0xA6h
1
0
1
0 0
1 1
0
QPI Initialization
0xA7h
1
0
1
0 0
1 1 1
QPI Initialization
0xA8h
1
0
1
0
1
0 0 0
QPI Initialization
0xA9h
1
0
1
0
1
0 0
1
QPI Initialization
0xAAh
1
0
1
0
1
0
1
0
QPI Initialization
0xABh
1
0
1
0
1
0
1 1
QPI Initialization
0xACh
1
0
1
0
1 1
0 0
QPI Initialization
0xADh
1
0
1
0
1 1
0
1
QPI Initialization
0xAEh
1
0
1
0
1 1 1
0
QPI Initialization
0xAFh
1
0
1
0
1 1 1 1
QPI Initialization
Integrated Memory Controller (IMC)
0xB0h
1
0
1 1
0 0 0 0
Memory Initialization of Integrated Memory Controller
0xB1h
1
0
1 1
0 0 0
1
Memory Initialization of Integrated Memory Controller
0xB2h
1
0
1 1
0 0
1
0
Memory Initialization of Integrated Memory Controller
0xB3h
1
0
1 1
0 0
1 1
Memory Initialization of Integrated Memory Controller
0xB4h
1
0
1 1
0
1
0 0
Memory Initialization of Integrated Memory Controller
0xB5h
1
0
1 1
0
1
0
1
Memory Initialization of Integrated Memory Controller
0xB6h
1
0
1 1
0
1 1
0
Memory Initialization of Integrated Memory Controller
0xB7h
1
0
1 1
0
1 1 1
Memory Initialization of Integrated Memory Controller
0xB8h
1
0
1 1 1
0 0 0 Memory Initialization of Integrated Memory Controller
0xB9h
1
0
1 1 1
0 0
1
Memory Initialization of Integrated Memory Controller
0xBAh
1
0
1 1
1 0 1 0 Memory Initialization of Integrated Memory Controller
0xBBh
1
0
1 1 1
0
1 1
Memory Initialization of Integrated Memory Controller
0xBCh
1
0
1 1 1 1
0 0
Memory Initialization of Integrated Memory Controller
0xBDh
1
0
1 1 1 1
0
1
Memory Initialization of Integrated Memory Controller
0xBEh
1
0
1 1 1 1 1
0 Memory Initialization of Integrated Memory Controller
0xBFh
1
0
1 1 1 1 1 1
Memory Initialization of Integrated Memory Controller
PCI Bus
0x50h 0
1
0
1
0 0 0 0 Enumerating PCI buses
0x51h 0
1
0
1
0 0 0
1
Allocating resources to PCI buses
0x52h 0
1
0
1
0 0
1
0 Hot Plug PCI controller initialization
0x53h 0
1
0
1
0 0
1 1
Reserved for PCI bus
0x54h 0
1
0
1
0
1
0 0 Reserved for PCI bus
0x55h 0
1
0
1
0
1
0
1
Reserved for PCI bus

Intel S5500WB Specifications

General

Brand	Intel
Model	S5500WB
Category	Server Board
Language	English