Intel S5500WB User Manual

Glossary Intel® Server Board S5500WB TPS
Revision 1.3
Intel order number E53971-004
100
Term Definition
HSC Hot-Swap Controller
HPA Host Physical Address
Hz Hertz (1 cycle / second)
I2C Inter-Integrated Circuit Bus
IA Intel
®
Architecture
IBF Input Buffer
ICH I/O Controller Hub
IC MB Intelligent Chassis Management Bus
IFB I/O and Firmware Bridge
ILM Independent Loading Mechanism
IMC Integrated Memory Controller
INTR Interrupt
IP Internet Protocol
IPMB Intelligent Platform Management Bus
IPMI Intelligent Platform Management Interface
IR Infrared
ITP In-Target Probe
KB 1024 bytes
KCS Keyboard Controller Style
LAN Local Area Network
LCD Liquid Crystal Display
LED Light Emitting Diode
LPC Low Pin Count
LUN Logical Unit Number
MAC Media Access Control
MB 1024KB
ME Management Engine
MD2 Message Digest 2 – Hashing Algorithm
MD5 Message Digest 5 – Hashing Algorithm – Higher Security
ms Milliseconds
MTTR Memory Type Range Register
Mux Multiplexor
NIC Network Interface Controller
NMI Nonmaskable Interrupt
OBF Output Buffer
OEM Original Equipment Manufacturer
Ohm Unit of electrical resistance
PECI Platform Environment Control Interface
PEF Platform Event Filtering
PEP Platform Event Paging
PIA Platform Information Area (This feature configures the firmware for the platform hardware)
PLD Programmable Logic Device
PMI Platform Management Interrupt
POST Power-On Self Test

Intel S5500WB Specifications

General

Brand	Intel
Model	S5500WB
Category	Server Board
Language	English