Quectel EG06 Series User Manual

LTE-A Module Series
EG06 Hardware Design
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3.17. PCIe Interface*
EG06 includes a PCIe interface which is compliant with PCI Express Specification Revision 2.1. The key
features of the PCIe interface are shown below:
 PCI Express Specification Revision 2.1 compliance
 Data rate at 5Gbps per lane
 Can be used to connect to an external Ethernet IC (MAC and PHY) or WLAN IC.
The following table shows the pin definition of PCIe interface.
Table 22: Pin Definition of the PCIe Interface
In order to enhance the reliability and availability in applications, please follow the criteria below in the
PCIe interface circuit design:
Pin Name
Pin No.
I/O
Description
Comment
Control Signal Part
PCIE_REF
CLK_P
179
AO
Output PCIe reference clock - plus
If unused, keep it open.
PCIE_REF
CLK_M
180
AO
Output PCIe reference clock - minus
If unused, keep it open.
PCIE_TX_M
182
AO
PCIe transmit - minus
If unused, keep it open.
PCIE_TX_P
183
AO
PCIe transmit - plus
If unused, keep it open.
PCIE_RX_M
185
AI
PCIe receive - minus
If unused, keep it open.
PCIE_RX_P
186
AI
PCIe receive -plus
If unused, keep it open.
PCIE_CLK_
REQ_N
188
IO
PCIe clock request
In master mode, it is an input
signal.
In slave mode, it is an output
signal.
If unused, keep it open.
PCIE_RST_N
189
IO
PCIe reset
In master mode, it is an
output signal.
In slave mode, it is an input
signal.
If unused, keep it open.
PCIE_WAKE
_N
190
IO
PCIe wake
In master mode, it is an input
signal.
In slave mode, it is an output
signal.
If unused, keep it open.

Quectel EG06 Series Specifications

General

Brand	Quectel
Model	EG06 Series
Category	Control Unit
Language	English