Quectel EG06 Series User Manual

LTE-A Module Series
EG06 Hardware Design
EG06_Hardware_Design 56 / 89
 Keep PCIe data and control signals away from sensitive circuits and signals, such as RF, audio, and
19.2MHz clock signals.
 A capacitance should be added in series on Tx/Rx traces to remove any DC bias.
 Keep the maximum trace length less than 300mm.
 The length difference of Tx or Rx differential pairs should be less than 0.7mm for PCIe routing traces.
 The differential impedance of PCIe data trace should be 100Ω±10%.
 Separate the SS-USB data pairs (Tx, Rx) and PCIe data pairs (Tx, Rx) from each other as far as
possible. If SS_USB and PCIe data pairs must cross on adjacent layers, please keep crossings at
right angles to minimize unbalanced (asymmetric) coupling.
 PCIe data traces must not be routed under components or crossing other traces.
“*” means under development.
3.18. WLAN Control Interface*
EG06 provides a low power PCIe interface* and a control interface for WLAN design.
The following table shows the pin definition of WLAN control interface.
Table 23: Pin Definition of WLAN Control Interface
Pin Name
Pin No.
I/O
Description
Comment
Coexistence and Control Signal Part
PM_ENABLE
5
DO
External power enable control
1.8V power domain
WAKE_ON_
WIRELESS
160
DI
Wake up the host (EG06 module)
by Wi-Fi module.
1.8V power domain
WLAN_EN
149
DO
WLAN function enable control.
Active high.
1.8V power domain
COEX_UART_RX
146
DI
LTE/WLAN coexistence signal
1.8V power domain
COEX_UART_TX
145
DO
LTE/WLAN coexistence signal
1.8V power domain
WLAN_SLP_CLK
169
DO
WLAN sleep clock
1.8V power domain
NOTE

Quectel EG06 Series Specifications

General

Brand	Quectel
Model	EG06 Series
Category	Control Unit
Language	English