R8C/1A Group, R8C/1B Group 18. Flash Memory
Rev.1.30 Dec 08, 2006 Page 267 of 315
REJ09B0252-0130
18.4.5 Full Status Check
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Table 18.6 lists the Errors and FMR0 Register Status. Figure 18.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
NOTE:
1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.
At the same time, the command code written in the first bus cycle is disabled.
Table 18.6 Errors and FMR0 Register Status
FRM0 Register
(Status Register) Status
Error Error Occurrence Condition
FMR07(SR5) FMR06(SR4)
1 1 Command
sequence
error
• When a command is not written correctly.
• When invalid data other than that which can be written
in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh).
(1)
• When the program command or block erase command
is executed while rewriting is disabled by the FMR02 bit
in the FMR0 register, or the FMR15 or FMR16 bit in the
FMR1 register.
• When an address not allocated in flash memory is input
during erase command input.
• When attempting to erase the block for which rewriting
is disabled during erase command input.
• When an address not allocated in flash memory is input
during write command input.
• When attempting to write the block for which rewriting
is disabled during write command input.
1 0 Erase error • When the block erase command is executed but
auto-erasure does not complete correctly.
0 1 Program error • When the program command is executed but not
auto-programming does not complete correctly.
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