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SPRUIS4A–December 2019–Revised May 2020
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Copyright © 2019–2020, Texas Instruments Incorporated
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.25 ENET Expansion Connector..................................................................................... 78
4.26 CSI Expansion Connector........................................................................................ 82
List of Figures
1 Thermal Caution ............................................................................................................. 6
2 J721E EVM Board........................................................................................................... 7
3 System Architecture Interface.............................................................................................. 8
4 J721E EVM Board Identification (SOM, CPB, QP Ethernet)........................................................... 9
5 J721E SOM Component Identification .................................................................................. 10
6 Jacinto7 Common Processor Component Identification .............................................................. 11
7 Quad Ethernet Component Identification ............................................................................... 12
8 Connector Used for Power Input......................................................................................... 13
9 Power ON/OFF Switch ................................................................................................... 14
10 Power ON/Fault LEDs ..................................................................................................... 15
11 Power Status LEDs ........................................................................................................ 16
12 EVM Push Buttons......................................................................................................... 18
13 EVM Configuration DIP Switch........................................................................................... 19
14 BOOT Switches Provided on the Processor Card ..................................................................... 22
15 JTAG Mux................................................................................................................... 24
16 J721E EVM Functional Block Diagram.................................................................................. 27
17 Quad Port Ethernet Expansion Functional Block diagram............................................................ 28
18 J721E SOM Power Distribution Block Diagram ........................................................................ 32
19 Power ON Sequencing .................................................................................................... 33
20 Voltage Supervisor Circuit ................................................................................................ 34
21 LPDDR4 IO Voltage Selection Circuit ................................................................................... 35
22 EVM Reset Architecture .................................................................................................. 39
23 EVM Clock Architecture ................................................................................................... 40
24 J721E SoC Primary Clock ................................................................................................ 41
25 J721E SoM LPDDR4 ...................................................................................................... 43
26 J721E SoM OSPI and Hyper Flash...................................................................................... 44
27 UFS Memory Block Diagram ............................................................................................. 45
28 eMMC Memory Block Diagram........................................................................................... 46
29 micro-SD Card Block Diagram ........................................................................................... 47
30 MCU Gigabit Ethernet Block.............................................................................................. 49
31 MCU Ethernet PHY Settings.............................................................................................. 50
32 Quad-SGMII Board I2C.................................................................................................... 52
33 QSGMII Ethernet PHY Settings .......................................................................................... 53
34 PCIe Interface for SERDES0 ............................................................................................. 54
35 PCIe SMBUS Block Diagram............................................................................................. 54
36 1L-PCIe Root Complex/Endpoint Selection Circuit .................................................................... 55
37 USB2.0 Header Connection .............................................................................................. 56
38 PCIe Interface for SERDES1 ............................................................................................. 57
39 2L-PCIe Root Complex/Endpoint Selection Circuit .................................................................... 57
40 PCIe Interface for SERDES2 ............................................................................................. 59
41 USB3.1 Type C Interface.................................................................................................. 60
42 Type C Power Delivery Current Settings................................................................................ 60
43 USB Hub Reference Clock Circuit ....................................................................................... 61
44 USB Hub Settings Circuit ................................................................................................. 61
45 USB1 ID Setting for HUB ................................................................................................. 61
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