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SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
46 MCU CAN0 Interface ...................................................................................................... 62
47 CAN Wake Push Button................................................................................................... 63
48 CAN Header Connections to DB9/Test Instrument.................................................................... 64
49 FPD-Link UB926 ID Setting Circuit ...................................................................................... 65
50 FPD-Link UB926 Mode Selection Circuit ............................................................................... 65
51 FPD-Link UB981 Device Settings Circuit ............................................................................... 66
52 Audio Port Interface Assignment......................................................................................... 68
53 Display Port Block Diagram............................................................................................... 69
54 MLB Interface Connector.................................................................................................. 70
55 ADC Interface Connector ................................................................................................. 71
56 RTC Block Diagram........................................................................................................ 72
57 Apple Authentication Block Diagram .................................................................................... 73
58 Expansion Board Interface Connectors ................................................................................. 74
59 CDCI I2C Isolation Circuit................................................................................................. 79
60 Dual I/O Voltage Selection for CSI Expansion Interface.............................................................. 82
List of Tables
1 REACH Compliance......................................................................................................... 7
2 Recommended External Power Supply ................................................................................. 13
3 Power LED Status.......................................................................................................... 15
4 Power LEDs................................................................................................................. 16
5 Power Test Points.......................................................................................................... 17
6 EVM Push Buttons......................................................................................................... 18
7 EVM Configuration Switch Function ..................................................................................... 20
8 EVM Configuration Switch Function ..................................................................................... 21
9 Wakup Boot Mode Switch (SW9) ........................................................................................ 22
10 Main Boot Mode Switch (SW8)........................................................................................... 22
11 UART Port Mapping ....................................................................................................... 23
12 JTAG 1:2 Mux selection................................................................................................... 24
13 TI 60 pin Connector (J16) Pinout ........................................................................................ 25
14 cTI20 Pin Connector (J1-Refer PROC081E2 SCH) Pinout........................................................... 26
15 TI14 Pin Connector (J2-Refer PROC081E2 SCH) Pinout ............................................................ 26
16 J721E EVM Interface Mapping........................................................................................... 29
17 J721E EVM I2C Table..................................................................................................... 30
18 J721E SoC - GPIO Mapping Table...................................................................................... 31
19 DDR I/O Voltage Selection................................................................................................ 35
20 J721E SoC S2R Logic Flow .............................................................................................. 36
21 J721E SoC S2R Logic Flow .............................................................................................. 36
22 INA Devices I2C Slave Address.......................................................................................... 37
23 External Power Monitor Header Pinouts ................................................................................ 38
24 Processor’s Secondary/SERDES Ref Clock ........................................................................... 42
25 EVM Peripheral Ref Clock ................................................................................................ 42
26 Board ID Memory Header Information .................................................................................. 48
27 Clock Source Selection.................................................................................................... 51
28 Reference Clock Selection for PCIe Host Operation .................................................................. 55
29 Reference Clock Selection for PCIe Endpoint Operation............................................................. 55
30 Resistors for Selecting PCIe Card Host or Device Operation........................................................ 56
31 Reference Clock Selection for PCIe Host Operation .................................................................. 58
32 Reference Clock Selection for PCIe Endpoint Operation............................................................. 58
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