CLKinX and PLLs Page
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SNAU145B–MAY 2013–Revised March 2018
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TICS Pro Usage
A.6 CLKinX and PLLs Page
The CLKinX and PLLs page allows entry of the input frequency at the different CLKinX pins, the mode by
which the active CLKinX is selected, where the CLKinX inputs are routed to.
This page also illustrates the frequencies that the PLL1 and PLL2 operate at. In distribution mode, the
CLKin1 frequency will directly be connected to the VCO/clock distribution path frequency. In addition to
the basic PLL dividers and controls, when the PLLX_NCLK_MUX selects the feedback mux as a source,
0-delay modes are achieved. When enabling 0-delay red text will help guide the user through properly
setting up 0-delay mode.
When using dual PLL mode, the OSCin Source combo box can be set to “External VCXO” which links the
OSCin frequency with the external VCXO frequency. When using single PLL2 mode, the OSCin Source
combo box can be set to “Independent” to allow the OSCin frequency to be unlinked from the external
VCXO frequency.
Figure 14. TICS Pro - CLKinX Control Page
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