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SYNC / SYSREF Page
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SNAU145B–MAY 2013–Revised March 2018
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Copyright © 2013–2018, Texas Instruments Incorporated
TICS Pro Usage
A.7 SYNC / SYSREF Page
The SYNC / SYSREF page allows some mode set buttons for JESD204B features. The SYNC dividers
button will stop all SYNC inputs, set normal SYNC mode, enable all dividers for SYNC, issue a SYNC by
toggling SYNC_POL, set all dividers to ignore SYNC, then return any other changed parameter to its
original state. This is a nice feature to ensure all outputs are synchronized together or to be run after
changing the digital delay value which requires a SYNC to update. This functionality is also available on
any other page through the toolbar as “SYNC Dividers.”
NOTE: To use SYNC or SYSREF, ensure that SYNC_EN = 1. To use SYSREF in continuous,
pulser, or re-clocked modes, be sure SYSREF_PD = 0.
The SCLKX_Y_DIS_MODE bits allow the clock outputs to be disabled or set to a low state. Because
values 1 and 2 are only conditionally set by the SYSREF_GBL_PD bit, it is possible to power up/down
several SYSREF outputs by programming only one register. When changing between 0x00 (Active) and
(0x01) Conditional Low, keeping the SYSREF_CLR = 1 during transition will prevent glitch pulses from the
SYSREF output.
Figure 15. TICS Pro - SYNC / SYSREF Page
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