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SNAU145B–MAY 2013–Revised March 2018
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Copyright © 2013–2018, Texas Instruments Incorporated
LMK04826 and LMK04828 User’s Guide
8. DCLKoutX_ADLYg_PD: If set, power down device clock glitchless analog delay feature.
9. DCLKoutX_ADLY_PD: If set, power down device clock analog delay.
10. DCLKoutX_ADLY: Analog delay (if enabled with #12).
11. DCLKoutX_ADLY_MUX: Enable duty cycle correct and half-step for this device clock divider.
12. DCLKoutX_MUX: Select source for CLKoutX. Can be Divider only, Divider+DCC+HS, Bypass, or
Analog Delay+Divider.
13. SDCLKoutY_POL: If set, polarity of SYSREF output clock is inverted.
14. DCLKoutX_POL: If set, polarity of device clock is inverted.
15. SYSREF_GBL_PD: Set the conditional for SDCLKoutY_DIS_MODE registers.
16. CLKoutX_Y_IDL: Increase input drive level to improve noise floor at cost of power.
17. CLKoutX_Y_ODL: Increase output drive level to improve noise floor at cost of power. No effect for
CLKoutX in bypass mode.
18. DCLKoutX_FMT: Set the clock output format for CLKoutX.
19. CLKoutX_Y_PD: Power down the entire CLKoutX_Y clock pair.
20. SDCLKoutY_DDLY: The SYSREF clock digital delay setting.
21. SDCLKoutY_HS: Set half step for the SYSREF output.
22. SDCLKoutY_ADLY_EN: Enable analog delay for the SYSREF clock path.
23. SDCLKoutY_ADLY: If enabled, set the analog delay for the SYSREF clock path.
24. SDCLKoutY_MUX: Select device clock or SYSREF clock path for CLKoutY.
25. SDCLKoutY_DIS_MODE: Set the output state of output clock drivers for the SYSREF clock. For
values of 1 and 2 works in conjunction with control on this list #15, SYSREF_GBL_PD.
26. SDCLKoutY_FMT: Set the clock output format for CLKoutY.
27. SDCLKoutY_PD: Power down the SYSREF clock path.
28. Clock output frequency for CLKoutX and CLKoutY.
NOTE: Setting a register equal to 0 OR un-checking a register’s checkbox performs the same
action. Similarly, setting a register equal to 1 is the same as checking that register’s
checkbox.
2.1.2 TICS Pro Tips
• Mousing over different controls will display some help prompt with the register address, data bit
location/length, and a brief register description in the lower left Context help pane.
2.2 SYSREF Quick Start
The LMK0482x EVK allows for verification of the LMK0482x’s implementation of JESD 204B SYSREF
functionality. To quickly setup and operate the SYSREF functions, refer to the following procedures.
2.2.1 Continuous SYSREF
1. On the Clock Outputs page, set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout).
2. Set SDCLKoutY_MUX = 1 (Set to “SYSREF” for desired SDCLKout).
3. On the SYNC/SYSREF page, set SYSREF_PD and SYSREF_DDLY_PD = 0.
4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout).
5. Perform a SYNC event (toggle SYNC_POL on/off/on).
6. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1.
7. Set SYSREF_MUX = 3 (SYSREF Continuous).
8. Ensure SYSREF_CLR = 0 (On the right side, in the grey Other SYNC Controls box).
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