Xilinx SmartLynq Plus User Manual

The connector has a 2-mm shrouded, keyed header. (See the Header Manufacturers table in
Chapter 8: GPIO Target Interface for Vendor part numbers.) Mang connectors for aaching the
high-performance ribbon cable to the JTAG port on a target board are available in both through-
hole and surface-mount conguraons.
Shrouded and keyed versions should always be used to guarantee proper orientaon when
inserng the cable. The connector requires 105 mm2 of board space. The target board voltage
applied to pin 2 of the JTAG connector is used as a power source for the output buers that
drive the output pins. Target interface connector details including dimensions, signal assignments,
pin descripons, vendor part numbers, DC electrical and switching characteriscs, and ming are
provided in the following tables and gures.
Figure 7: Dimensions and Signal Assignments
7.59 mm
6.30 mm
12.00 mm
2.00 mm
4
6
8
10
12
14
2
TYP.
16.66 mm
0.50 mm
2.00 mm
1
3
5
7
9
11
13
NC
GND
GND
GND
GND
GND
PGND
VREF
JTAG
TMS
TCK
TDO
TDI
NC
SRSTn
X25141-022321
Table 1: Interface Pin Descriptions
Pin
Number
Pin Name Direction Description
2 V
REF
In Target Reference Voltage. Connected to a voltage bus on the target board
that serves the JTAG interface.
4 TMS Out JTAG Test Mode Select. JTAG mode signal establishing appropriate TAP
state transitions on all target JTAG devices.
6 TCK Out JTAG Test Clock. Clock signal for JTAG operations connected to the TCK pin
on all target JTAG devices sharing the same data stream.
8 TDO In JTAG Test Data Out. Serial data stream received from the TDO pin on the
last device in a JTAG chain.
Chapter 7: JTAG Target Interface
UG1514 (v1.0) March 8, 2021 www.xilinx.com
SmartLynq Module+ 22
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Xilinx SmartLynq Plus Specifications

General

Brand	Xilinx
Model	SmartLynq Plus
Category	Network Hardware
Language	English