Xilinx SmartLynq Plus User Manual

Table 1: Interface Pin Descriptions (cont'd)
Pin
Number
Pin Name Direction Description
10 TDI Out JTAG Test Data In. Outputs the serial data stream transmitted to the TDI
pin on the first device in a JTAG chain.
13 PGND Out JTAG Pseudo Ground. Use of this pin is optional, if unused it can be left with
no connection. PGND is LOW during JTAG operation.
14 SRST Out System Reset. Use of this pin is optional, if unused it can be left with no
connection. Host applications can customize the behavior of this signal.
Table 2: Mating Connectors for 2 mm pitch, 14-Conductor Ribbon Cable
Manufacturer SMT, Vertical
Through-Hole,
Vertical
Through-Hole,
Right Angle
Website
Molex 87832-1420 87831-1420 87833-1420 www.molex.com
Table 3: DC Electrical Characteristics
Symbol Description Conditions Min. Max. Unit
V
OH
High-level output voltage
V
REF
= 1.65V, I
OH
= –8 mA 1.2
- VV
REF
= 2.3V, I
OH
= –9 mA 1.7
V
REF
= 3V, I
OH
= –12 mA 2.3
V
OL
Low-level output voltage
I
OL
= 8 mA
-
0.4
VI
OL
= 9 mA 0.5
I
OL
= 12 mA 0.7
V
IH
High-level input voltage
V
REF
= 1.2V to 1.35V 0.78
- V
V
REF
= 1.35V to 1.65V 0.88
V
REF
= 1.65V to 1.95V 1.1
V
REF
= 1.95V to 2.7V 1.6
V
REF
= 2.7V to 3.3V 2
V
IL
Low-level input voltage
V
REF
= 1.2V to 1.95V
-
0.4
V
V
REF
= 1.95V to 2.7V 0.7
V
REF
= 2.7V to 3.3V 0.8
I
CC
Dynamic current - - 110 mA
Table 4: Switching Characteristics
Symbol Description Conditions Min. Max. Unit
T
CLK
Clock period with 50% duty cycle 50 kHz to 100 MHz 10 8,000 ns
T
CPD
Cable Propagation Delay Time (TDI or TMS
relative to the negative edge of TCK)
V
REF
= 1.2V to 3.3V - 1 ns
T
TSU
Cable Setup Time (TDO relative to the negative
edge of TCK)
V
REF
= 1.2V to 3.3V 1 - ns
Chapter 7: JTAG Target Interface
UG1514 (v1.0) March 8, 2021 www.xilinx.com
SmartLynq Module+ 23
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Xilinx SmartLynq Plus Specifications

General

Brand	Xilinx
Model	SmartLynq Plus
Category	Network Hardware
Language	English