Xilinx SmartLynq Plus User Manual

The <direcon> is an 8-bit hexadecimal value. Bits set to 1 in the <direcon> eld are set as
outputs. Otherwise the pin is used as an input. The second oponal value argument is used for
specifying how to drive the pins that are set as outputs. Note that seng the direcon to 0x
makes all pins outputs. The following is an example of how to use this command when logged in
over ssh:
sudo /opt/xilinx/bin/update_hw_gpio 0x3f 0xe7
This does the following:
•
<direcon> 0x3f sets pin 0 to 5 as outputs; 6 and 7 as inputs
•
<value> 0xef sets the output values: pin 0 = 1, pin 1 = 1, pin 2 = 1, pin 3 = 0, pin 4 = 0, pin 5 =
1
Chapter 8: GPIO Target Interface
UG1514 (v1.0) March 8, 2021 www.xilinx.com
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Xilinx SmartLynq Plus Specifications

General

Target Interface	JTAG
Storage Temperature	-20°C to 70°C
Host Interface	USB 2.0
Status Indicators	LED
Supported Devices	Xilinx FPGAs and SoCs
Compatibility	Windows, Linux
Interface	USB

Summary

Revision History

Chapter 1: Overview

Features

The SmartLynq+ Module provides several key features for debug and trace operations.

Description

Explains the SmartLynq+ Module's high-bandwidth connectivity for system debug and trace.

Physical Description

Describes the physical enclosure of the SmartLynq+ module and its heat sink assembly.

Chapter 2: Connectors

Host Side

Details the DC power, USB 3.0, and Ethernet connectors located on the left side.

Target Side

Describes the GPIO, JTAG, HSDP, and MICTOR connectors on the right side of the module.

Front View

Details the reset pin, mode selector switch, and micro-SD card slot on the front panel.

Chapter 3: Installing the SmartLynq+ Module

Chapter 4: USB 3.0 Host Connection

Minimum Host System Requirements

Lists the supported operating systems and processor architectures for host systems.

Default USB 3.0 IP Setting

Specifies the default IP address (10.0.0.2) for the SmartLynq+ Module's USB 3.0 interface.

Windows USB 3.0 Driver Setup

Step-by-step guide to associate the RNDIS driver with the SmartLynq+ Module on Windows.

Linux USB 3.0 Setup

Instructions for configuring the network interface on Linux using ifconfig command.

Changing the USB 3.0 IP Setting

Procedure to modify the default USB 3.0 IP address using a network configuration file.

Chapter 5: Ethernet Connection

Changing the Ethernet IP Settings

Steps to configure static IP addresses for the Ethernet connection via SSH.

Chapter 6: SmartLynq+ Module Display

Chapter 7: JTAG Target Interface

Dimensions and Signal Assignments

Details connector dimensions, signal assignments, and pin descriptions for JTAG.

Chapter 8: GPIO Target Interface

GPIO Connector

Describes the 2x6 GPIO connector, pinout, and power requirements for 8-bit operations.

Chapter 9: HSDP Target Interface

HSDP Connector

Details the USB-C receptacle connector, its pins, and the HSDP interface implementation.

High Speed Differential Pairs

Covers electrical requirements for high-speed differential pairs used in HSDP.

Configuration Channel (CC) Connections

Explains how CC lines detect orientation and power sense for USB-C cable connection.

Versal ACAP Connectivity

References for VCK190 schematics and guidelines for 10 Gb/s HSDP connectivity.

Chapter 10: Parallel Debug Interface

Signal Descriptions

Details the function, direction, and pull-up/down configurations for MICTOR connector pins.

Appendix A: Regulatory and Compliance Information

Appendix B: Additional Resources and Legal Notices

Xilinx Resources

Provides links to Xilinx support resources like Answers, Documentation, Downloads, and Forums.

Documentation Navigator and Design Hubs

Information on using DocNav and Design Hubs to access Xilinx documents, videos, and resources.

References

Lists supplemental material and documents useful for understanding this guide.