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Avnet Electronics Marketing 2 of 28 Rev D 24 Apr 2015
Contents
1 Introduction ..................................................................................................................................................... 4
1.1 Description ............................................................................................................................................... 4
1.2 Board Features .......................................................................................................................................... 5
1.3 Reference Designs .................................................................................................................................... 6
1.4 Ordering Information ............................................................................................................................... 7
2 Functional Description .................................................................................................................................... 8
2.1 Xilinx Spartan-6 FPGA LX9 FPGA ........................................................................................................ 9
2.2 Clocks ..................................................................................................................................................... 11
2.2.1 Triple Output User programmable Texas Instruments CDCE913 clock ........................................ 11
2.2.2 Optional 66.6 MHz Maxim low-cost, fixed-frequency oscillator ................................................... 11
2.3 Memory .................................................................................................................................................. 12
2.3.1 32 Mb x 16 (64MB) Micron LPDDR Mobile SDRAM component ............................................... 13
2.3.2 128 Mb Micron Multi-I/O SPI Flash .............................................................................................. 15
2.4 Communication ...................................................................................................................................... 16
2.4.1 Universal Serial Bus (USB) 2.0, Full Speed USB-to-JTAG bridge via Atmel AT90USB162 /
ATMEGA162U2 AVR Microcontroller and TE Connectivity USB-A connector ....................................... 16
2.4.2 USB-UART..................................................................................................................................... 16
2.4.3 10/100 Ethernet PHY via Texas Instruments DP83848J PHY and TE Connectivity RJ45 connector
17
2.5 User I/O and Expansion Connectors ...................................................................................................... 19
2.5.1 Peripheral Module (PMOD) ........................................................................................................... 19
2.6 User Interfaces ........................................................................................................................................ 20
2.6.1 User LEDs ....................................................................................................................................... 20
2.6.2 Four configurable FPGA user DIP switches (TE Connectivity 1571983-4) .................................. 20
2.6.3 One configurable FPGA user push-button (TE Connectivity 8-1437565-0) .................................. 20
2.7 Power ...................................................................................................................................................... 21
2.7.1 Power Good LED ............................................................................................................................ 21
2.7.2 FPGA Decoupling ........................................................................................................................... 22
2.7.3 Power Results.................................................................................................................................. 23
2.8 Configuration ......................................................................................................................................... 24
2.8.1 Configuration Modes ...................................................................................................................... 24
2.8.2 Digilent On-board JTAG Boundary Scan Configuration ............................................................... 24
2.8.3 Multi-I/O SPI Flash Configuration ................................................................................................. 24
2.8.4 JTAG Chain .................................................................................................................................... 24
3 Test Design .................................................................................................................................................... 25
4 Acknowledgements ....................................................................................................................................... 26
5 Getting Help and Support .............................................................................................................................. 27
6 Revision History ............................................................................................................................................ 28
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