Xilinx Virtex-7 FPGA VC7222 IBERT User Manual

64 www.xilinx.com VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Chapter 3: Creating the GTZ IBERT Core
11. In the Program Manager window, under Program and Debug, click Generate
Bitstream. Confirm the launching of implementation (Figure 3-12).
12. When the Bitstream Generation Completed dialog window appears, click Cancel
(Figure 3-12).
13. Navigate to
..\ibert_7series_gtz_0\ibert_7series_gtz_0_example\ibert_7serie
s_gtz_0_example.runs\impl_1 directory to locate the generated bitstream.
X-Ref Target - Figure 3-12
Figure 3-12: Generate Bitstream
X-Ref Target - Figure 3-13
Figure 3-13: Bitstream Generation Completed
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Xilinx Virtex-7 FPGA VC7222 IBERT Specifications

General

Brand	Xilinx
Model	Virtex-7 FPGA VC7222 IBERT
Category	Motherboard
Language	English