ZC706 Evaluation Board User Guide www.xilinx.com 19
UG954 (v1.5) September 10, 2015
Feature Descriptions
D6 PL_DDR3_A10 SSTL15 107 A10/AP
B7 PL_DDR3_A11 SSTL15 84 A11
H12 PL_DDR3_A12 SSTL15 83 A12_BC_N
A10 PL_DDR3_A13 SSTL15 119 A13
G11 PL_DDR3_A14 SSTL15 80 A14
C6 PL_DDR3_A15 SSTL15 78 A15
F8 PL_DDR3_BA0 SSTL15 109 BA0
H7 PL_DDR3_BA1 SSTL15 108 BA1
A7 PL_DDR3_BA2 SSTL15 79 BA2
L1 PL_DDR3_D0 SSTL15 5 DQ0
L2 PL_DDR3_D1 SSTL15 7 DQ1
K5 PL_DDR3_D2 SSTL15 15 DQ2
J4 PL_DDR3_D3 SSTL15 17 DQ3
K1 PL_DDR3_D4 SSTL15 4 DQ4
L3 PL_DDR3_D5 SSTL15 6 DQ5
J5 PL_DDR3_D6 SSTL15 16 DQ6
K6 PL_DDR3_D7 SSTL15 18 DQ7
G6 PL_DDR3_D8 SSTL15 21 DQ8
H4 PL_DDR3_D9 SSTL15 23 DQ9
H6 PL_DDR3_D10 SSTL15 33 DQ10
H3 PL_DDR3_D11 SSTL15 35 DQ11
G1 PL_DDR3_D12 SSTL15 22 DQ12
H2 PL_DDR3_D13 SSTL15 24 DQ13
G5 PL_DDR3_D14 SSTL15 34 DQ14
G4 PL_DDR3_D15 SSTL15 36 DQ15
E2 PL_DDR3_D16 SSTL15 39 DQ16
E3 PL_DDR3_D17 SSTL15 41 DQ17
D4 PL_DDR3_D18 SSTL15 51 DQ18
E5 PL_DDR3_D19 SSTL15 53 DQ19
F4 PL_DDR3_D20 SSTL15 40 DQ20
F3 PL_DDR3_D21 SSTL15 42 DQ21
D1 PL_DDR3_D22 SSTL15 50 DQ22
D3 PL_DDR3_D23 SSTL15 52 DQ23
A2 PL_DDR3_D24 SSTL15 57 DQ24
B2 PL_DDR3_D25 SSTL15 59 DQ25
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont ’d)
XC7Z045 (U1)
Pin
Net Name I/O Standard
DDR3 SODIMM Memory J1
Pin Number Pin Name