Power and Environmental Specifications Intel
®
Server Board S5500BC TPS
Intel order number: E42249-003 Revision 1.0
72
Table 35. Voltage Regulation Limits
Parameter Tolerance Minimum Nominal Maximum Units
+ 3.3V - 5% / +5% +3.14 +3.30 +3.46 V
rms
+ 5V - 5% / +5% +4.75 +5.00 +5.25 V
rms
+ 12V - 5% / +5% +11.40 +12.00 +12.60 V
rms
- 12V - 5% / +9% -11.40 -12.00 -13.08 V
rms
+ 5VSB - 5% / +5% +4.75 +5.00 +5.25 V
rms
8.2.7 Dynamic Loading
The output voltages should remain within the limits for the step loading and capacitive loading
specified in the following table. The load transient repetition rate should be tested between 50
Hz and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is a test
specification. The step load may occur anywhere within the MIN load to the MAX load
conditions.
Table 36. Transient Load Requirements
Output
Step Load Size
1
Load Slew Rate Test Capacitive Load
+3.3 V 6.0 A
0.25 A/sec 250 F
+5 V 4.0 A
0.25 A/sec 400 F
12 V 18.0 A
0.25 A/sec 2200 F 1, 2
+5 VSB 0.5 A
0.25 A/sec 20 F
Notes:
1. The +12 V should be tested with 2200 F evenly divided between the four +12 V rails.
2. Step loads on each 12 V output may occur simultaneously.
8.2.8 Capacitive Loading
The power supply should be stable and meet all capacitive loading requirements. The following
table outlines these conditions.
Table 37. Capacitive Loading Conditions
8.2.9 Closed-Loop Stability
The power supply should be unconditionally stable under all line/load/transient load conditions,
including capacitive load ranges. A minimum of 45° phase margin and -10 dB gain margin is
Output Minimum Maximum Units
+3.3 V 250 6,800
F
+5 V 400 4,700
F
+12 V 500 each 11,000
F
-12 V 1 350
F
+5 VSB 20 350
F