AWARD
®
BIOS Setup
3-13
Note: Change these settings only if you are familiar with the chipset.
DRAM Timing by SPD
Selects whether DRAM timing is configured by reading the contents of the
SPD (Serial Presence Detect) device on the DRAM module. Setting to
Enabled makes both DRAM Cycle Length and DRAM Clock automatically
determined by BIOS according to the configurations on the SPD.
SDRAM Cycle Length
The option controls the CAS latency, which determines the timing delay
before SDRAM starts a read command after receiving it. Settings are Auto, 2
and 3 (clock cycles). 2 increases system performance while 3 provides more
stable system performance. Auto allows BIOS to determine the best CAS
latency length.
Advanced Chipset Features
↑ ↓ → ←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
DRAM Timing by SPD Yes
SDRAM Cycle Length Auto
DRAM Clock Auto
Memory Hole Disabled
P2C/C2P Concurrency Enabled
Fast R-W Turn Around Enabled
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
Frame Buffer Size 8M
AGP Aperture Size 64M
OnChip USB Enabled
USB Keyboard Support Disabled
OnChip Sound Auto
OnChip Modem Auto
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
PCI Master 0 WS Write Enabled
PCI Delay Transaction Enabled
PCI#2 Access #1 Retry Enabled
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
Memory Parity/ECC Check Disabled
CMOS Setup Utility - Copyright(C) 1984-2000 Award Software
Advanced Chipset Features
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