Circuit-, IC descriptions and list of abbreviations
EN 138 DVDR615/699.
Clock Distribution
Figure 9-6 Chrysalis Clock
The Chrysalis [7800] has a complex clock system, which is
needed to support the processes running at different
frequencies such as video decoding, audio decoding or
peripheral I/O devices etc. To ensure a synchronous
initialization of all the registers and state machines, all the PLLs
are switched to their default frequency and the reset sequence
is run at 4MHz. Then when the booting control unit is correctly
initialized and once it has captured all the booting parameters,
it sets the PLLs to its functional frequency to allow the modules
to run at their nominal frequencies. Thanks to a clock blocking
mechanism, the frequency switching is glitch free.
System clocks:
• PNX7100 [7800], pins AF9 and AF10 : 4MHz provided by
the crystal oscillator [7804]
• SAA7118 [7007], pins A3 and B4 : 24.576 MHz provided by
crystal [1002]
• SDRAM [7902] and [7903], pin 38 : 133MHz provided by
PNX7100
• 1394-LINK [7001], pin 88 : 49.152MHz provided by 1394-
PHY
• 1394-PHY [7000], pin 59 and 60 : 24.576MHz provided by
crystal [1001]
Memory
Several memories are used on the Chrysalis [7800]:
• EEPROM [7904] : this memory contains all the necessary
boot parameters of the board
• EEPROM [7905] : this memory contains all the necessary
parameters for the application
• FLASH [7900] : this memory contains the application,
diagnosis and service software
Reset
Figure 9-7 Chrysalis reset
VIP7118
7007
CHRYSALIS
PNX7100
7800
SDRAM
FRONTEND INTERFACE
7902
133MHz
SDRAM
7903
1394 LINK
7001
AUDIO PLL
7924
1394 PHY
24.576 MHz
24.576 MHz
7000
4 MHz
CHRYSALIS
PNX7100
7800
GPIO
PNX7100_Resetn
PNX7100_SYS_Resetn
7926
3V3dig
>1
EJTAG_Resetn
IResetDig
NCP303
7923-1
&
7923-4
&
Reset_IDEn
7923-2
&
Reset_1394n
7923-3
&
Analog_Reset
VIP_Resetn
3V3dig
CL 36532004_005.eps
140203
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