Quectel LPWA Series User Manual

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
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4.6.4. MAIN_RI*
AT+QCFG= “risignaltype”,“physical” can be used to configure MAIN_RI behavior. No matter on which
port a URC is presented, the URC will trigger the behavior of MAIN_RI pin.
Table 26: Pin Definition of MAIN_RI
The default MAIN_RI behaviors can be configured flexibly by AT+QCFG="urc/ri/ring"*. Refer to
document [2] for details. The default behavior of the MAIN_RI is shown as below.
Table 27: Default Behaviors of MAIN_RI
4.7. GRFC Interfaces*
The module provides two generic RF control interfaces for the control of external antenna tuners.
Table 28: Pin Definition of GRFC Interfaces
Pin Name
Pin No.
I/O
Description
Comment
MAIN_RI
39
DO
Main UART ring indication
1.8 V power domain.
If this pin is unused, keep this pin open.
State
Response
Idle
MAIN_RI keeps at high level.
URC
MAIN_RI outputs 120 ms low pulse in case of a new URC returns.
A URC can be outputted from the main UART interface (default), the CLI UART or the debug UART
through configuration via AT+QURCCFG.
Pin Name
Pin No.
I/O
Description
Comment
GRFC1
83
DO
Generic RF controller
1.8 V power domain.
If these pins are unused, keep them
open.
GRFC2
84
DO
Generic RF controller
NOTE

Quectel LPWA Series Specifications

General

Brand	Quectel
Model	LPWA Series
Category	GSM/GPRS Modules
Language	English