PROGRAM
INTERRUPT
INTRODUCTION
PROCESSOR
STATES
Processing State P 1
Interrupt Response
State P 2
Interrupt Control
State
P
3
Machine
Condition
State P 4
•
Program
interrupts
occur
as
a
result
of
errors
in
data
or
instruction
specifications,
input/output
operations,
external
signals, equipment mal-
functions
or
arithmetic
errors.
The
instruction
being executed
at
the
time
of
the
interrupt
can be completed, suppressed,
or
terminated
depending on
the
cause
of
the
interrupt.
An
interrupt
can be inhibited
or
permitted
in
any
state
through
pro-
gramming.
If
an
interrupt
occurs
and
is permitted, conditions
existing
in
the
interrupted
state
are
automatically stored. Control is
then
passed to
the
Interrupt
Control
State
P 3
or
Machine Condition
State
P
4,
depending
on
the
cause
of
the
interrupt.
(See
Processor
States
below.)
The
priority
of
the
interrupt
is established and
an
analysis is made to
determine
the
proper
linkage
to
the
Interrupt
Response
State
P2
so
that
the
interrupt
may
be processed.
After
interrupt
processing is completed, control is
returned
to
the
state
which was
last
interrupted,
and
normal processing
is resumed.
If
several
interrupts
occur
at
the
same time,
the
one
having
the
highest
priority
is processed. The
remaining
interrupts
are
processed
in
turn,
depending on
their
priority.
• The RCA 70/46 Processor
has
four
processor
states
that
provide control
of
system
and
program
interrupts.
Programs
can be executed in
anyone
of
the
states, because each
state
is completely independent
and
has
its
own
set
of
registers.
The
processor
states
and
their
functions
are
as
follows:
• The Processing
State
PI
interprets
and
executes
the
user's
program.
This processing
state
is
the
problem-oriented
state.
• The
Interrupt
Response
State
P
2
performs
specific
program
tasks
as
dictated
by
the
Interrupt
Control
State
P
3.
• The
Interrupt
Control
State
P
3
is automatically
entered
when
an
inter-
rupt
that
is
other
than
one caused by a machine check
or
power
failure
is recognized.
In
this
state,
programming
is responsible
for
performing
a
detailed analysis
of
the
cause of
the
interrupt
and
establishing
its
priority.
After
these functions
are
performed, linkage is provided to
the
related
interrupt
processing routine
in
the
Interrupt
Response
State
P
2
•
•
The
Machine Condition
State
P
4
is entered whenever a machine check,
scratch
pad memory
parity
error
(if
applicable),
or
power
failure
occurs.
In
this
state,
programming
analyzes
the
cause
of
a machine
interrupt
and
establishes
its
priority. Control is then
transferred
to
the
Interrupt
Response
State
P
2
,
so
that
an
indication
of
the
cause
of
interrupt
can
be
given to
the
operator.
16
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