Assembly /Status
Register
CBA Register
INPUT/OUTPUT
INSTRUCTIONS
Start Device Instruction
Block 1
Block 2
Input/Output Operation
Data
Bytes
I
Standard
Device Byte I
o
23
24
31
Bit
Positions 0 through 31
are
for
equipment use only.
When
the
device
status
is stored as a
result
of
an
input/output
opera-
tion,
bit
positions 24
through
31
of
the
assembly/status
register
are
used
to
store
the
standard
device byte. The
bits
of
the
standard
device
byte
supply
status
information
pertaining
to
the
device control electronics
and
the
input/output
device
and
are
defined
as
follows:
Bit
24 -
External
Device Request
Interrupt
Pending
Bit
25 -
Terminating
Interrupt
Pending
Bit
26 - Device Busy
Bit
27 - Control Busy
(not
applicable)
Bit
28 - Device
End
Bit
29 - Second
Indicator
Bit
30 - Device Inoperable
Bit
31 -
Status
Modifier
(For
a detailed description
of
the
above, see
Standard
Device Byte
section, page 65.)
•
Not
modified by channel, equals CBA originally fetched
from
76-79.
•
There
are
four
processor
instructions
which
are
concerned
with
input/
output
operations. They
are
Start
Device,
Halt
Device, Check Channel
and
Test
Device. These
instructions
are
executed by
the
processor
and
the
results, in
the
form
of
condition codes,
are
available upon
instruction
com-
pletion.
It
should be noted
that
the
condition code
settings
indicate
the
results
of
the
instruction
and
not
the
results
of
the
input/output
operation
that
the
instruction
may
be initiating. The channel continues off-line to
accomplish
the
input/output
operation
as
specified by
the
instruction.
However,
during
this
time
the
processor continues executing subsequent
instructions.
• The
Start
Device
instruction
is a privileged operation and, therefore,
can
be executed only
if
the
mode
bit
(bit
position 15
of
the
Interrupt
Status
register
for
the
current
state)
is
set
to zero. This
instruction
is executed
in
the
normal
mode. Continuation
of
progranl
execution is delayed
until
the
Start
Device
instruction
has
been terminated.
Upon execution
of
a
Start
Device instruction,
the
following events
occur.
(See figure 5.)
•
If
the
privileged mode
bit
(bit
position 15
of
the
Interrupt
Status
register)
for
the
current
state
is
not
set
to zero,
the
privileged operation
bit
is
set
in
the
Interrupt
Flag
register
and
an
interrupt
occurs
(if
permi
tted)
.
•
If
the
specified channel is a selector channel
that
is
not
available on
the
system,
the
condition code is
set
to 3,
the
Start
Device
instruction
is
terminated
and
program
control is
transferred
to
the
next
instruction.
The
input/output
operation
is
not
initiated.
47
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