Interrupt Flag Register
(Cont'd)
INTERRUPT
CONDITIONS
INTERRUPT
MECHANIZATION
Automatic Interrupt
Block 1
Progra~
Interrupt
can
be
used
to
cancel
the
interrupt
condition
when
it
occurs.
The
second
mask
is
composed of
bits
2
30
through
227
of
the
32-bit
Interrupt
Mask
register
asso-
ciated
with
the
state
in
which
the
processor
is
operating.
If
the
Program
Mask
prohibits
the
interrupt
it
is
cancelled.
If
the
Program
Mask
permits
the
interrupt,
the
Interrupt
Mask
register
is
scanned. Like
all
the
other
interrupt
conditions,
the
masks
of
the
32-bit
Interrupt
Mask
register
leave
these
four
interrupt
conditions
pending
if
the
associated
mask
bits
are
zeros.
• A description
of
the
individual
interrupt
conditions is given in
table
9.
More detailed
information
concerning
the
interrupt
conditions is given
in
the
instruction
descriptions. Some
interrupt
conditions
arise
from
input/
output
channel operations,
and
these conditions
are
further
discussed
in
the
Input/Output
Operational Control section.
Notes:
1. When
an
interrupt
condition occurs,
the
current
instruction
can be
suppressed
or
it
can be terminated. When
an
instruction
is sup-
pressed,
the
condition code
setting
that
existed before
the
instruc-
tion
was
attempted
remains
unchanged.
Data
in
main
memory
and
the
general
registers
specified by
the
instruction
also
remain
un-
changed. When
an
instruction
is
terminated,
the
condition code
setting
and
data
in
the
general
registers
and/or
main
memory
are
un
predictable.
2. When
operating
with
T =
0,
program
interrupt
functions described
in
the
70/35, 70/45, 70/55 Processor Reference Manual apply.
When
operating
with
T =
1,
program
interrupt
functions
of
table 9 apply.
•
There
are
two ways
of
causing a change
of
processor state. They
are:
1.
Auto~atic
Interrupt:
effected when
any
interrupt
condition de-
scribed
in
table 9 occurs,
and
is permitted.
2.
Progra~
Controlled
Interrupt:
effected when a
Program
Control
instruction
is executed.
Whenever
the
processor
state
is changed,
either
by
automatic
inter-
rupt
or
by
the
execution of a
Program
Control instruction, some machine
conditions
must
be stored
in
the
P
counter
and
the
Interrupt
Status
reg-
ister
of
the
terminated
state
for
possible use when
the
state
is
initiated
again.
In
addition,
certain
machine conditions associated
with
the
state
being
initiated
must
be
extracted
from
the
P
counter
and
the
Interrupt
Status
register
of
the
new state.
All
the
storing
and
extracting
required when processor
status
are
changed is accomplished by
hardware.
•
When
an
automatic
interrupt
condition occurs,
the
following events
occur:
(See figure 3.)
• A check is made to see
if
the
interrupt
condition is one
of
the
following
four:
23
Significance
Error
Exponent
Underflow
Decimal
Overflow
Fixed-Point
Overflow
To Next Page
Loading...
Need help?
General
