Channel Command
Register-II (CCR-II)
(Cont'd)
Channel Command
Register-I (CCR-I)
Input/Output
Operation
Bit
3 - Skip flag
(SKIP)
Bit
4 -
Program
controlled
interrupt
flag
(PCI)
Bit
Positions 5 through 7
are
reserved
for
future
use.
Bit
Positions 8 through
15
contain
the
channel
status
byte. The bits
of
the
channel
status
byte
are
generated
as
a result
of
the
input/output
operation
and
are
defined as follows:
Bit
8 -
Program
Controlled
Interrupt
Bit
9 - Incorrect Length
Bit
10-Program
Check
Bit
11-
Protection Check
Bit
12 - Channel
Data
Check
Bit
13
- Channel Control Check
Bit
14 - Reserved
for
use by
the
processor
Bit
15 - Termination
Interrupt
(For
a detailed description of
the
above see Channel
Status
Byte
section, page 61.)
Bit
Positions
16
through 31 contain
the
number
of bytes of
main
memory
to
or
from which
data
is
transferred.
This information is obtained
from
the
Channel Command Word. The count can
range
from
0 bytes to
65,536 bytes. When
the
I/O
is terminated, these
bit
positions contain
the
remaining
byte
count
(if
any).
Command
Data
Address
of
First
Byte
or
Location
of
new CCW
0000
Code
if
Command
is
Transfer
in
Channel
o 3 4
7 8
31
Bit
Positions 0 through 3
are
used by
the
processor.
It
should be noted
that
these bits
are
used in
the
channel command word
as
modifier bits.
Once
the
command has been initiated
and
the
entire
8-bit command code
has
been
sent
to
the
specified device control electronics, these bits
are
used
by
the
processor. They no longer contain
the
modifier bits.
Bit
Positions
4-
through 7 contain
the
command code. This code is
obtained
from
the channel command word. The commands
are
defined
as
follows:
Read
(0101)
Write
(0011)
Write Control (0111)
Sense (0001)
Read Reverse (0010)
Write
Erase
(0100)
Transfer
in
Channel (1001)
Bit
Positions 8 through 31 contain
the
address of
the
initial byte in
main memory
at
which the operation begins;
or
contains
the
branch
address
if
the
command is a
Transfer
in Channel. This information is
obtained
from
the Channel Command Word.
46
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