Specification
Protection
Privileged Operation
Operation
Code Trap
•
An
address
error
interrupt
occurs
when:
Privileged
Instructions
1. A Load Scratch
Pad
or
Store Scratch
Pad
instruction specifies a
first
or
second address which is not on a word boundary.
2.
Bits 28
through
31
of
the
second operand
of
a Set Storage Key
or
Insert
Storage Key instruction
are
not zero.
3. The memory protect
feature
is not installed
and
the
protection key
in
the
Interrupt
Status
register
for
the
current
program
state
is
not
zero.
In
these
error
interrupt
conditions,
the
operation is suppressed. The
data
in
main
memory
and
registers is unchanged.
•
An
address
error
interrupt
occurs when the storage key
and
the
protec-
tion key
of
the
result location
do
not match. The operation is terminated.
The
result
data
is unpredictable. (This
interrupt
can occur only
if
the
memory protect
feature
is installed.)
• A privileged operation
interrupt
occurs
if
execution of
any
privileged
instruction
is
attempted
and
the non-privileged mode
bit
(bit
position 15
in
the
Interrupt
Status
register)
for
the
current
state
is
1.
The operation
is
suppressed
and
the
condition code, registers,
and
main
memory
are
unaltered.
•
An
operation code
trap
interrupt
occurs
under
the following conditions:
1. The memory protect
feature
is not installed
and
an
attempt
to
execute a
Set
Storage Key
or
Insert
Storage Key instruction is made.
2. The direct control
feature
is
not
installed
and
an
attempt
to execute
a
Write
Direct
or
Read Direct instruction is made.
89
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