R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 228 of 315
REJ09B0252-0130
Figure 16.47 Example of Register Setting in Master Receive Mode (I
2
C bus Interface Mode)
End
RDRF = 1 ?
Master receive mode
No
Yes
(1) Set the TEND bit to 0 and set to master receive
mode.
Set the TDRE bit to 0.
(1,2)
(2) Set the ACKBT bit to the transmit device.
(1)
(3) Dummy read the ICDRR register
(1)
(4) Wait for 1 byte to be received.
(5) Judge (last receive - 1).
(6) Read the receive data.
(7) Set the ACKBT bit of the last byte and set to disable the
continuous receive operation (RCVD = 1).
(2)
(8) Read the receive data of (last byte - 1).
(9) Wait until the last byte is received.
(10) Set the STOP bit to 0.
(11) Generate the stop condition.
(12) Wait until the stop condition is generated.
(13) Read the receive data of the last byte.
(14) Set the RCVD bit to 0.
(15) Set to slave receive mode.
ICCR1 register TRS bit ← 0
Dummy read in ICDRR register
Read RDRF bit in ICSR register
Last receive
- 1 ?
ICSR register TEND bit ← 0
ICSR register STOP bit ← 0
ICCR2 register SCP bit ← 0
BBSY bit
← 0
Read STOP bit in ICSR register
STOP = 1 ?
ICSR register TDRE bit ← 0
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(12)
(10)
(13)
(14)
(11)
(9)
(15)
ICIER register ACKBT bit ← 0
No
Yes
Read ICDRR register
ICIER register ACKBT Bit ← 1
ICCR1 register RCVD Bit ← 1
Read ICDRR register
Read RDRF bit in ICSR register
RDRF = 1 ?
Read ICDRR register
ICCR1 register RCVD bit ← 0
ICCR1 register MST bit ← 0
No
Yes
Yes
NOTES:
1. Do not generate the interrupt while processing steps (1) to (3).
2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7).
Processing step (8) is dummy read of the ICDRR register.
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