ST STM8 User Manual

Single wire interface module (SWIM) UM0470
16/39 DocID14024 Rev 4
3.7 CPU register access
The CPU registers are mapped in the STM8 memory, and they can be read or written
directly using the ROTF and the WOTF SWIM commands. the write operations to the CPU
registers are committed only when the CPU is stalled.
To flush the instruction decode phase, the user must set the FLUSH bit in the DM
control/status register 2 (named DM_CSR2) after writing a new value in the program
counter (PCE, PCH, PCL) Refer to
Section 4.12.10 on page 33) for more details.
3.8 SWIM communication in Halt mode
To maintain the communication link with the debug host, the HSI oscillator remains ON
when the MCU enters the Halt mode. This means that Halt mode power-consumption
measurements have no meaning when the SWIM is active.
In Halt mode, the user can access the SWIM module but not the DEBUG module. The
NO_ACCESS bit in the SWIM_CSR register is set when the system is in HALT, WFI or
readout protection mode. It means that in this case, no connection is accessible between
the SWIM module and the DEBUG module nor between the rest of the STM8 systems.
The OSCOFF bit in the SWIM_CSR register is used to switch off the HSI oscillator. In this
case, any access to the SWIM module is lost as long as the device is in Halt mode and that
the SWIM pin is high. The only way to recover the debug control is to induce a falling edge
on the SWIM pin: this will re-enable the HSI oscillator.
Table 2. CPU register memory mapping in STM8 MCUs
CPU register Memory location
A 7F00h
PCE 7F01h
PCH 7F02h
PCL 7F03h
XH 7F04h
XL 7F05h
YH 7F06h
YL 7F07h
SPH 7F08h
SPL 7F09h
CC 7F0Ah

ST STM8 Specifications

General

Architecture	8-bit
Core	STM8
ADC Resolution	10-bit
Max CPU Frequency	24 MHz
Flash Memory	Up to 128 KB
RAM	Up to 6 KB
EEPROM	Up to 2 KB
I/O Pins	Up to 68
Operating Voltage	2.95V to 5.5V
Operating Temperature	-40°C to 85°C
Communication Interfaces	UART, SPI, I2C
Package Options	SO, TSSOP, LQFP, UFQFPN

Summary

Introduction

Debug System Overview

Communication Layer

Single Wire Interface Module (SWIM)

3.1 Operating Modes

Describes the different operating modes of the SWIM interface: OFF, I/O, and ACTIVE.

3.2 SWIM Entry Sequence

Details the specific sequence required to activate the SWIM interface from the OFF state.

3.3 Bit Format

Explains the return-to-zero bit format used for SWIM communication.

3.3.1 High Speed Bit Format

Defines the bit encoding for high-speed communication with 10 SWIM clock pulses.

3.3.2 Low Speed Bit Format

Defines the bit encoding for low-speed communication with 22 SWIM clock pulses.

3.4 SWIM Communication Protocol

Outlines the protocol for host-to-target and target-to-host communication.

3.5 SWIM Commands

Details the available commands for controlling the SWIM interface.

3.5.1 SRST: System Reset

Describes the SRST command for generating a system reset.

3.5.2 ROTF: Read On-the-Fly

Explains the ROTF command for reading data from memory while the CPU is running.

3.5.3 WOTF: Write On-the-Fly

Details the WOTF command for writing data to memory while the CPU is running.

3.6 SWIM Communication Reset

Explains how to reset the SWIM communication in case of problems.

3.7 CPU Register Access

Describes how to access CPU registers using SWIM commands.

3.8 SWIM Communication in Halt Mode

Explains SWIM operation and limitations when the MCU is in Halt mode.

3.9 Physical Layer

Details the physical characteristics and timings of the SWIM interface.

3.10 STM8 MCUs SWIM Registers

Provides information on the SWIM registers used for control and status.

3.10.1 SWIM Control Status Register (SWIM_CSR)

Describes the bits and functionality of the SWIM_CSR register.

3.10.2 SWIM Clock Control Register (CLK_SWIMCCR)

Details the CLK_SWIMCCR register for controlling the SWIM clock.

Debug Module (DM)

4.1 Introduction

Introduces the Debug Module (DM) for performing debugging tasks without an emulator.

4.2 Main Features

Lists the primary capabilities of the Debug Module.

4.3 Debug

Covers the debugging functionalities provided by the DM.

4.3.1 Reset

Explains how breakpoints are used to initialize the debug session.

4.3.2 Breakpoints

Describes how the DM generates stalls when breakpoints are reached.

4.3.3 Abort

Details the procedure for using the abort function via the STALL bit.

4.3.4 Watchdog Control

Explains how to configure watchdogs to stop when the CPU is stalled.

4.3.5 Interaction with SWIM

Describes how the DM status is communicated via the SWIM interface.

4.4 Breakpoint Decoding Table

Provides a table for decoding breakpoint interrupt generation conditions.

4.5 Software Breakpoint Mode

Details how to insert breakpoints using software break instructions.

4.6 Timing Description

Defines when the debug module stalls the CPU based on breakpoint sources.

4.7 Abort

Explains how the stall is generated immediately when writing the STALL bit.

4.8 Data Breakpoint

Describes when a stall is generated for data breakpoints.

4.9 Instruction Breakpoint

Explains how DM stalls the CPU before instruction execution for instruction breakpoints.

4.10 Step Mode

Details how the STM8 CPU stall is activated before instruction execution in step mode.

4.11 Application Notes

Provides notes on illegal memory access, forbidden stack access, and DM breaks.

4.11.1 Illegal Memory Access

Explains how to detect illegal memory access using breakpoint conditions.

4.11.2 Forbidden Stack Access

Describes using DM to prevent overwriting critical stack data or instructions.

4.11.3 DM Break

Explains how to continue program execution after a DM break.

4.12 DM Registers

Lists and describes the read/write registers of the Debug Module.

4.12.1 DM Breakpoint Register 1 Extended Byte (DM_BKR1E)

Defines the DM_BKR1E register for breakpoint 1 extended address bits.

4.12.2 DM Breakpoint Register 1 High Byte (DM_BKR1H)

Defines the DM_BKR1H register for breakpoint 1 high address bits.

4.12.3 DM Breakpoint Register 1 Low Byte (DM_BKR1L)

Defines the DM_BKR1L register for breakpoint 1 low address bits.

4.12.4 DM Breakpoint Register 2 Extended Byte (DM_BKR2E)

Defines the DM_BKR2E register for breakpoint 2 extended address bits.

4.12.5 DM Breakpoint Register 2 High Byte (DM_BKR2H)

Defines the DM_BKR2H register for breakpoint 2 high address bits.

4.12.6 DM Breakpoint Register 2 Low Byte (DM_BKR2L)

Defines the DM_BKR2L register for breakpoint 2 low address bits.

4.12.7 DM Control Register 1 (DM_CR1)

Describes the DM_CR1 register for controlling watchdog and breakpoints.

4.12.8 DM Control Register 2 (DM_CR2)

Details the DM_CR2 register for vector table remapping and other controls.

4.12.9 DM Control/Status Register 1 (DM_CSR1)

Explains the DM_CSR1 register for step mode and breakpoint flags.

4.12.10 DM Control/Status Register 2 (DM_CSR2)

Details the DM_CSR2 register for software breakpoint and stall control.

4.12.11 DM Enable Function Register (DM_ENFCTR)

Describes the DM_ENFCTR register for freezing peripherals during debug.

4.12.12 Summary of SWIM, DM and Core Register Maps

Provides a summary of STM8 MCU registers including SWIM and DM.

Appendix A: DM_ENFCTR Register Description by STM8 Product