Debug module (DM) UM0470
22/39 DocID14024 Rev 4
4.3 Debug
The DM registers can be read and written only through the SWIM interface. The STM8 core
has no access to these registers.
4.3.1 Reset
Once the SWIM is active and that the SWIM_DM bit is set in the SWIM_CSR register, a
‘data read’ breakpoint at the reset vector address is automatically set, due to the reset
values of the debug module registers. This breakpoint can be used to initialize the debug
session.
4.3.2 Breakpoints
The DM generates a stall to the core when a breakpoint is reached. When the processor is
stalled, the host can read or modify any address in memory. Access to the processor
registers is explained in
Table 3.7: CPU register access on page 16.
To restart the program execution, the STALL bit in the DM_CSR2 must be cleared using the
WOTF command of the SWIM protocol.
4.3.3 Abort
To use the abort function, the host must write the STALL bit in the DM_CSR2 using the
SWIM WOTF command.
No interrupt is generated. The core is stalled in the current state. Using the SWIM
commands, the host can read and modify the status of the MCU. Use the procedure
described in
Section 3.7: CPU register access if the CPU registers must be modified.
The host can restart the program execution by resetting the STALL bit using the SWIM
commands.
4.3.4 Watchdog control
Using the WDGOFF bit in the DM control register 1 (DM_CR1) (see Section 4.12.7 on page
30) the user can configure the window watchdog and the independent watchdog counters to
be stopped while the CPU is stalled by the debug module. This bit must be set before the
watchdogs are activated. If a watchdog is enabled by the hardware watchdog option bit, the
WDGOFF bit has no effect on it.
4.3.5 Interaction with SWIM
The SWIM sends the status bit which indicates if the SWIM is active or not. When the SWIM
is not active, the DM does not generate any break/stall request to the CPU.
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