Revision history UM0470
38/39 DocID14024 Rev 4
Revision history
Table 7. Document revision history
Date Revision Changes
15-Jan-2008 1 Initial release.
10-Dec-2009 2
Updated documentation references in Introduction.
Section 3.2: SWIM entry sequence: updated Figure 4 and
explanation.
Section 3.3: Bit format: replaced OBL bit with HSIT bit.
Added Appendix A.
06-Jun-2011 3
Introduction: updated titles of reference documents.
Updated name of ‘IOM’ bit to SWIM disable bit (SWD) in Section 3.1:
Operating modes, Figure 3, and SWIM control status register
(SWIM_CSR).
Updated name of ‘MCR’ register to ‘CFG_GCR’ register in
Section 3.1: Operating modes.
24-Aug-2016 4
Updated sections:
Section 3.2: SWIM entry sequence
Section 3.3: Bit format
Section 3.6: SWIM communication reset
Section 3.8: SWIM communication in Halt mode
Updated figures format:
Figure 1: Debug system block diagram
Figure 2: SWIM pin external connections
Figure 3: SWIM activation sequence
Figure 5: SWIM entry sequence
Figure 6: High speed bit format
Figure 7: Low speed bit format
Figure 8: Command format (host -> target)
Figure 9: Data format (target -> host)
Figure 11: Debug module block diagram
Figure 12: STM8 MCU instruction model
Figure 13: STM8 Debug module stall timing
Figure 14: STM8 DM data breaktiming
Figure 15: STM8 DM instruction break timing
Figure 16: STM8 DM step timing
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