Jd75\
______
_
~
945423-9701
Bit Number
7
16
,
17
16
Table 3-3. Model 911 VDT Controller Addressable
Output
Bits
Description
NOTE
The following descriptions
of
the CRU bit functions assume that word select has
been set to logic
O.
Display Memory Write Data
~
represent an ASCII character that
is
to
be
written into
the screen refresh memory. The destination
of
the character
is
determined by the con-
tents
of
the cursor address register. Bit 0
is
the least significant bit, and bit 6
is
the
most significant bit
of
the character. The 7-bit character and the high/low intensity bit
are written into the cursor address when the write data strobe
is
output.
The least significant four bits
of
memory write data (CRU bits
0-3
for VDT 0 and
CRU bits 10-13 for VDT 1) have special Significance when self-test mode
is
activated.
Bits
0 and 1 (or bits 10 and 11) select one to four test inputs. The selected input
is
read
as
the CRU input signal previous state flag or self-test signal. Table 3-2 shows the
characteristics
of
the test inputs. Bits 2 and 3 (or bits
12
and 13) program the input
to the keyboard test transmitter. The transmitter
output
feeds the keyboard input cir-
cuit to simulate keyboard data. Table
34
relates the state
of
the control bits to the
character generated by the transmitter.
Dual Intensity
~
selects the high or low intensity level for VDT display. Logic 0
selects high intensity display; logic 1 selects low intensity display when the dual
intensity feature
is
active.
On
the Japanese model, this bit selects either the alpha-
numeric or the Katakana mode. A logic 0 selects alphanumeric; a logic 1 selects Kata-
kana.
All
characters are displayed at high intensity.
Write Data Strobe
~
causes the contents
of
the display memory write data register and
the dual intensity bit
to
be written into memory at the location specified
by
the
cursor address register.
Test Mode
~
logic 1 selects test mode. A logic 0
output
returns the control unit
to
the
normal operation mode. Activating test mode does the following:
• Turns on the test mode indicator
• Tests the keyboard receiver with a serial test pattern
• Selects one
of
four key controller signals for input on the previous state/self-
test input line.
Keyboard data test patterns are selected by decoding write data bits 2 and 3 (or
12
and 13). Table
34
correlates keyboard data test patterns with select bits.
As
shown in
table 3-2, write data bits
0 and 1 (or 10 and 11) select one
of
the
follOWing
signals:
•
Video
•
Horizontal sync
•
Vertical sync
•
Audio alarm.
3-9
Digital Systems Division
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