Xilinx ML505 User Manual

14 www.xilinx.com ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Chapter 1: ML505/ML506/ML507 Evaluation Platform
R
Block Diagram
Figure 1-1 shows a block diagram of the ML50x Evaluation Platform (board).
Related Xilinx Documents
Prior to using the ML50x Evaluation Platform, users should be familiar with Xilinx
resources. See Appendix C, “References” for direct links to Xilinx documentation. See the
following locations for additional documentation on Xilinx tools and solutions:
• EDK: www.xilinx.com/edk
• ISE: www.xilinx.com/ise
• Answer Browser: www.xilinx.com/support
• Intellectual Property: www.xilinx.com/ipcenter
Figure 1-1: Virtex-5 FPGA ML50x Evaluation Platform Block Diagram
Virtex-5
LXT/SXT/FXT
FPGA
UG347_03_110807
GPIO
(Button/LED/DIP Switch)
PLL Clock Generator
Plus User Oscillator
System Monitor
SMA
(Differential In/Out Clocks)
Dual PS/2
GTP: PCIe 1x
Flash
Sync
SRAM
Platform Flash
SPI
System ACE
Controller
CPLD
Misc. Glue Logic
SelectMap SPI Cfg BPI Flash Cfg
Slave Serial
JTAG
JTAG
JTAG
JTAG
Master Serial
XGI Header
USB
Controller
10/100/1000
Ethernet PHY
AC97
Audio CODEC
Battery and
Fan Header
CF PC4
RS-232 XCVR
VGA Input
Codec
16 X 32
Character LCD
IIC EEPROM
RJ-45
Line Out /
Headphone
Digital Audio
Mic In / Line In
Serial
Piezo/Speaker
Host
Peripheral
Peripheral
16
32
16
32
3216
User IIC Bus
DDR2
SO-DIMM
DVI-I Video Out
DVI Output
Codec
GTP: 2 Serial ATA
GTP: 4 SFP
GTP: 4 SMA
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Xilinx ML505 Specifications

General

Brand	Xilinx
Model	ML505
Category	Motherboard
Language	English