Xilinx ML505 User Manual

36 www.xilinx.com ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Chapter 1: ML505/ML506/ML507 Evaluation Platform
R
Configuration Address [2:0] allows the user to select among multiple configuration
images. For System ACE configuration, up to eight possible configurations can be stored
on a CF card. The Platform Flash PROM and Linear Flash can hold up to four separate
bitstreams that can be chosen by Configuration Address [2:0].
Mode[2:0] selects the FPGA configuration mode according to Table 1-18.
32. Encryption Key Battery
An onboard rechargeable lithium battery is connected to the V
BATT
pin of the FPGA to
hold the encryption key for the FPGA.
33. SPI Flash
The ML50x board has a 32-Mb SPI Flash (ST Microelectronics M25P32). The SPI Flash can
be used for FPGA configuration or to hold user data. The SPI Flash can be in-system
programmed using a Xilinx download cable with flying leads attached to header J2
(Figure 1-6).
Table 1-18: Configuration Mode DIP Switch Settings
Mode[2:0] Mode
000 Master Serial (Platform Flash PROM, up to four configurations)
001 SPI (One configuration)
010 BPI Up (Parallel NOR Flash, up to four configurations)
011 BPI Down (Parallel NOR Flash, up to four configurations)
100 Master SelectMAP (Platform Flash PROM, up to four configurations)
101 JTAG (PC4, System ACE up to eight configurations)
110 Slave SelectMAP (Platform Flash PROM, up to four configurations)
111 Slave Serial (Platform Flash PROM, up to four configurations)
Figure 1-6: J2 SPI Flash Programming Header
SPI Prog
TDI
J2
1
TMS
INIT
TCK
TDO
VCC3V3
GND
UG347_09_021407
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Xilinx ML505 Specifications

General

Brand	Xilinx
Model	ML505
Category	Motherboard
Language	English