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Xilinx ML505 User Manual
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58
www
.xilinx.com
ML505/ML506/ML507
Ev
aluation Platform
UG347 (v3.1.1) October 7, 20
09
R
7.
T
o finish pr
ogramming the chip, cycle the power
by turning off
the board powe
r
switch.
8.
After
turning the board
back on, verify that the clock fr
equencies ar
e corr
ect.
Figure B-2:
Programming th
e IDT5V9885 on the ML50
x
Using iMP
ACT
UG
3
47_
a
pdx_
a
_01_112706
Downloaded from
Elcodis.com
electronic components distributor
57
59
Table of Contents
Default Chapter
5
Table of Contents
5
Preface: about this Guide
7
Guide Contents
7
Additional Documentation
7
Additional Support Resources
8
Typographical Conventions
8
Online Document
9
Overview
11
Features
11
Package Contents
13
Additional Information
13
Block Diagram
14
Related Xilinx Documents
14
Detailed Description
15
1 Virtex-5 FPGA
17
Configuration
17
I/O Voltage Rails
17
2 Ddr2 Sodimm
18
MIG Compliance
18
DDR2 Memory Expansion
19
DDR2 Clock Signal
19
DDR2 Signaling
19
Digitally Controlled Impedance
18
3 Differential Clock Input and Output with SMA Connectors
19
4 Oscillators
19
5 LCD Brightness and Contrast Adjustment
20
6 GPIO DIP Switches (Active-High)
20
7 User and Error Leds (Active-High)
21
8 User Pushbuttons (Active-High)
22
9 CPU Reset Button (Active-Low)
22
10 XGI Expansion Headers
22
Differential Expansion I/O Connectors
22
Single-Ended Expansion I/O Connectors
23
Other Expansion I/O Connectors
24
11 Stereo AC97 Audio Codec
26
12 RS-232 Serial Port
27
13 Character X 2-Line LCD
27
14 IIC Bus with 8-Kb EEPROM
27
506 DVI Connector
27
16 PS/2 Mouse and Keyboard Ports
28
17 System ACE and Compactflash Connector
28
18 ZBT Synchronous SRAM
30
19 Linear Flash Chips
30
20 Xilinx XC95144XL CPLD
30
100 /1000 Tri-Speed Ethernet PHY
31
22 USB Controller with Host and Peripheral Ports
32
23 Xilinx XCF32P Platform Flash PROM Configuration Storage Devices
32
24 JTAG Configuration Port
33
25 Onboard Power Supplies
33
26 AC Adapter and Input Power Switch/Jack
34
27 Power Indicator LED
34
28 Done Led
35
29 Init Led
35
30 Program Switch
35
31 Configuration Address and Mode DIP Switches
35
32 Encryption Key Battery
36
33 SPI Flash
36
34 IIC Fan Controller and Temperature/Voltage Monitor
37
35 Piezo
37
36 VGA Input Video Codec
37
37 JTAG Trace/Debug
38
CPU Debug Description
38
CPU JTAG Header Pinout
41
CPU JTAG Connection to FPGA
41
38 Rotary Encoder
42
39 Differential GTP/GTX Input and Output with SMA Connectors
42
40 PCI Express Interface
43
41 Serial-ATA Host Connectors
44
42 SFP Connector
44
43 GTP/GTX Clocking Circuitry
46
Overview
46
Frequency Synthesizer for SFP/SMA GTP/GTX Transceiver Clocking
46
SATA GTP/GTX Transceiver Clock Generation
47
SGMII / Loopback GTP/GTX Transceiver Clock Generation
47
44 Soft Touch Landing Pad
48
45 System Monitor
49
IIC Buses
52
Configuration Options
53
JTAG (Xilinx Download Cable and System ACE Controller) Configuration
53
Platform Flash PROM Configuration
54
Linear Flash Memory Configuration
54
SPI Flash Memory Configuration
54
Appendix A: Board Revisions
55
Appendix B: Programming the IDT Clock Chip
57
Overview
57
Downloading to the Ml50X Board
57
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Xilinx ML505 Specifications
General
Brand
Xilinx
Model
ML505
Category
Motherboard
Language
English
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