Xilinx ML605 Hardware User's Guide

ML605 Hardware User Guide www.xilinx.com 53
UG534 (v1.9) February 26, 2019
Detailed Description
User DIP Switch
The ML605 includes an active-High eight pole DIP switch as described in Figure 1-20 and
Table 1-23.
Table 1-22: User Pushbutton Switch Connections
U1 FPGA Pin Schematic Net Name
Pushbutton
Switch Pin
A19 GPIO_SW_N SW5.2
A18 GPIO_SW_S SW6.2
G17 GPIO_SW_E SW7.2
H17 GPIO_SW_W SW8.2
G26 GPIO_SW_C SW9.2
H10 CPU_RESET SW10.2
X-Ref Target - Figure 1-20
Figure 1-20: User 8-pole DIP Switch
UG534_20_072109
GPIO DIP SW1
GPIO DIP SW2
GPIO DIP SW3
GPIO DIP SW4
GPIO DIP SW5
GPIO DIP SW6
GPIO DIP SW7
GPIO DIP SW8
1
2
3
4
5
6
7
8
16
SW1
VCC1V5
SDMX-8-X
15
14
13
12
11
10
9
67
8 9 10 2 3 4 5
RP7
4.7K 6
RP7
4.7K 6
RP7
4.7K 6 1
RP7 RP7
4.7K 1
RP7
4.7K 1
RP7
4.7K 1
RP7
4.7K 4.7K
5% 5% 5% 5% 5% 5% 5% 5%
Table 1-23: User DIP Switch Connections
U1 FPGA Pin Schematic Net Name DIP Switch Pin
D22 GPIO_DIP_SW1 SW1.1
C22 GPIO_DIP_SW2 SW1.2
L21 GPIO_DIP_SW3 SW1.3
L20 GPIO_DIP_SW4 SW1.4
C18 GPIO_DIP_SW5 SW1.5
B18 GPIO_DIP_SW6 SW1.6
K22 GPIO_DIP_SW7 SW1.7
K21 GPIO_DIP_SW8 SW1.8
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Xilinx ML605 Specifications

General

Brand	Xilinx
Model	ML605
Category	Motherboard
Language	English