Xilinx ML605 Hardware User's Guide

ML605 Hardware User Guide www.xilinx.com 83
UG534 (v1.9) February 26, 2019
Appendix C
Xilinx Design Constraints
Overview
The Xilinx Design Constraints (UCF) file template provides for designs targeting the
ML605 evaluation board. Net names in the constraints correlate with net names on the
latest ML605 evaluation board schematic. Identify the appropriate pins and replace the net
names with net names in the user RTL.
See the
Constraints Guide (UG625) [Ref 25] for more information.
The FMC connectors J63 (LPC) and J64 (HPC) are connected to 2.5V Vcco banks. Because
each user’s FMC card implements customer-specific circuitry, the FMC bank I/O
standards must be uniquely defined by each customer.
Note: The latest version of the Xilinx constraint file can be found on the Virtex-6 FPGA
ML605 Evaluation Kit website.
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Xilinx ML605 Specifications

General

Brand	Xilinx
Model	ML605
Category	Motherboard
Language	English