ZC706 Evaluation Board User Guide www.xilinx.com 3
UG954 (v1.5) September 10, 2015
04/24/2013 1.2
Chapter 1, ZC706 Evaluation Board Features: Table 1-1 feature descriptions are now
linked to their respective sections in the book. Figure 1-2, Figure 1-33, and
Figure 1-34 were replaced. Table 1-2 was removed because it was a duplicate of
Table 1-11. Table 1-2: Switch SW11 Configuration Option Settings was added. FMC
Connector JTAG Bypass, page 33 was updated. Default lane size information below
Figure 1-17 was changed. Figure 1-18 PCI Express Lane Size Select Jumper J19 was
added. The names of pins 18 and 19 changed in Table 1-17. The address of I
2
C bus
PMBUS_DATA/CLOCK changed in Table 1-25. Reference designator DS35 was added
to Ta ble 1-27. Callout numbers in the User I/O, page 57 section are now linked to
Table 1-1. SW13 information was added to the section User Pushbuttons, page 59.
In Table 1-33, J5 pin H22 changed to XC7Z045 (U1) pin AH26 and H23 changed to
AH27. The section ZC706 Board Power System, page 72 was added. Voltage levels
were changed in VADJ Voltage Control, page 79. Table 1-37 was modified and
Table 1-38 was added.
Appendix A, Default Switch and Jumper Settings: The SW11 selection in Table A-1
changed.
Appendix G, Regulatory and Compliance Information: A link to the master answer
record was added.
07/31/2013 1.3
Updated Table 1-22. Replaced the master User Constraints File (UCF) list in
Appendix C, Master Constraints File Listing with the master Xilinx Design
Constraints (XDC) list. Updated references throughout the document.
04/28/2015 1.4
Updated “LMZ22000 Family Regulator Description” to LMZ31500 and LMZ31700
Family Regulator Description. Updated Table 1-4, Table 1- 7, Table 1-13, Table 1-23,
Table 1-28 through Table 1-30, Table 1-32 through Table 1-34, Table 1-36, and
Table A-2. Added Figure A-1. Updated Appendix C, Master Constraints File Listing.
09/10/2015 1.5
Updated J48 header jumper setting (third row in Table 1-7).
Date Version Revision
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